forked from github/verilator
verilator_gantt: Fix reading broken /cpu/procinfo reports
This commit is contained in:
Wilson Snyder
parent
f5c9deecb8
commit
2560fc867f
@ -271,16 +271,18 @@ def report_cpus():
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socket = None
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if cpu in Global['cpuinfo']:
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socket = int(Global['cpuinfo'][cpu]['physical_id'])
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Global['cpu_sockets'][socket] += 1
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print(" socket=%d" % socket, end='')
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cpuinfo = Global['cpuinfo'][cpu]
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if 'physical_id' in cpuinfo and 'core_id' in cpuinfo:
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socket = int(cpuinfo['physical_id'])
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Global['cpu_sockets'][socket] += 1
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print(" socket=%d" % socket, end='')
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core = int(Global['cpuinfo'][cpu]['core_id'])
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Global['cpu_socket_cores'][str(socket) + "__" + str(core)] += 1
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print(" core=%d" % core, end='')
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core = int(cpuinfo['core_id'])
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Global['cpu_socket_cores'][str(socket) + "__" + str(core)] += 1
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print(" core=%d" % core, end='')
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model = Global['cpuinfo'][cpu]['model_name']
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if model:
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if 'model_name' in cpuinfo:
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model = cpuinfo['model_name']
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print(" %s" % model, end='')
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print()
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53
test_regress/t/t_gantt_io_arm.dat
Normal file
53
test_regress/t/t_gantt_io_arm.dat
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@ -0,0 +1,53 @@
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VLPROFTHREAD 1.1 # Verilator thread profile dump version 1.1
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VLPROF arg --threads 4
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VLPROF arg +verilator+prof+threads+start+1
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VLPROF arg +verilator+prof+threads+window+2
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VLPROF stat yields 51
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VLPROFPROC processor : 0
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VLPROFPROC model name : Phytium,FT-2500/128
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VLPROFPROC BogoMIPS : 100.00
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VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
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VLPROFPROC CPU implementer : 0x70
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VLPROFPROC CPU architecture: 8
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VLPROFPROC CPU variant : 0x1
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VLPROFPROC CPU part : 0x663
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VLPROFPROC CPU revision : 3
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VLPROFPROC
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VLPROFPROC processor : 1
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VLPROFPROC model name : Phytium,FT-2500/128
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VLPROFPROC BogoMIPS : 100.00
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VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
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VLPROFPROC CPU implementer : 0x70
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VLPROFPROC CPU architecture: 8
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VLPROFPROC CPU variant : 0x1
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VLPROFPROC CPU part : 0x663
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VLPROFPROC CPU revision : 3
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VLPROFPROC
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VLPROFPROC processor : 2
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VLPROFPROC model name : Phytium,FT-2500/128
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VLPROFPROC BogoMIPS : 100.00
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VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
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VLPROFPROC CPU implementer : 0x70
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VLPROFPROC CPU architecture: 8
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VLPROFPROC CPU variant : 0x1
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VLPROFPROC CPU part : 0x663
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VLPROFPROC CPU revision : 3
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VLPROFPROC
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VLPROFPROC processor : 3
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VLPROFPROC model name : Phytium,FT-2500/128
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VLPROFPROC BogoMIPS : 100.00
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VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
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VLPROFPROC CPU implementer : 0x70
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VLPROFPROC CPU architecture: 8
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VLPROFPROC CPU variant : 0x1
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VLPROFPROC CPU part : 0x663
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VLPROFPROC CPU revision : 3
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VLPROFPROC
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VLPROF eval start 57709 elapsed 1745979 cpu 2 on thread 1
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VLPROF eval_loop start 58532 elapsed 1744353 cpu 2 on thread 1
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VLPROF mtask 85 start 90465 elapsed 64569 predict_start 14315 predict_cost 30533 cpu 2 on thread 1
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VLPROF mtask 79 start 156555 elapsed 137754 predict_start 44848 predict_cost 48001 cpu 2 on thread 1
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VLPROF mtask 90 start 77352 elapsed 1159 predict_start 14315 predict_cost 21592 cpu 3 on thread 2
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VLPROF mtask 81 start 79799 elapsed 868 predict_start 35907 predict_cost 29215 cpu 3 on thread 2
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VLPROF mtask 87 start 81746 elapsed 887 predict_start 65147 predict_cost 33809 cpu 3 on thread 2
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VLPROF stat ticks 180832
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37
test_regress/t/t_gantt_io_arm.out
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37
test_regress/t/t_gantt_io_arm.out
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@ -0,0 +1,37 @@
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Verilator Gantt report
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Argument settings:
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+verilator+prof+threads+start+1
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+verilator+prof+threads+window+2
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--threads 4
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Analysis:
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Total threads = 2
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Total mtasks = 5
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Total cpus used = 2
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Total yields = 51
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Total evals = 1
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Total eval loops = 1
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Total eval time = 294309 rdtsc ticks
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Longest mtask time = 137754 rdtsc ticks
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All-thread mtask time = 205237 rdtsc ticks
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Longest-thread efficiency = 46.8%
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All-thread efficiency = 34.9%
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All-thread speedup = 0.7
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Prediction (what Verilator used for scheduling):
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All-thread efficiency = 82.4%
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All-thread speedup = 1.6
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Statistics:
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min log(p2e) = -1.054 from mtask 79 (predict 48001, elapsed 137754)
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max log(p2e) = 3.641 from mtask 87 (predict 33809, elapsed 887)
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mean = 1.656
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stddev = 2.104
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e ^ stddev = 8.200
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CPUs:
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cpu 2: cpu_time=202323 Phytium,FT-2500/128
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cpu 3: cpu_time=2914 Phytium,FT-2500/128
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Writing profile_threads.vcd
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20
test_regress/t/t_gantt_io_arm.pl
Executable file
20
test_regress/t/t_gantt_io_arm.pl
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(dist => 1);
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run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt"
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. " $Self->{t_dir}/$Self->{name}.dat > gantt.log"],
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check_finished => 0);
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files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename});
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ok(1);
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1;
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