Fix slice extraction from packed array, bug717.

Changes

@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix internal error on "input x =" syntax error, bug716. [Lane Brooks]
 
+****  Fix slice extraction from packed array, bug717. [Jan Egil Ruud]
+
 ****  Fix inside statement EQWILD error, bug718. [Jan Egil Ruud]
 
 

src/V3WidthSel.cpp

@@ -393,8 +393,15 @@ private:
 	AstNodeDType* ddtypep = fromdata.m_dtypep;
 	VNumRange fromRange = fromdata.m_fromRange;
 	if (ddtypep->castBasicDType()
+	    || ddtypep->castPackArrayDType()
 	    || (ddtypep->castNodeClassDType()
 		&& ddtypep->castNodeClassDType()->packedUnsup())) {
+	    int elwidth = 1;
+	    AstNode* newwidthp = widthp;
+	    if (AstPackArrayDType* adtypep = ddtypep->castPackArrayDType()) {
+		elwidth = adtypep->width() / fromRange.elements();
+		newwidthp = new AstConst (nodep->fileline(),AstConst::Unsized32(), width * elwidth);
+	    }
 	    AstNode* newlsbp = NULL;
 	    if (nodep->castSelPlus()) {
 		if (fromRange.littleEndian()) {
@@ -415,9 +422,12 @@ private:
 	    } else {
 		nodep->v3fatalSrc("Bad Case");
 	    }
+	    if (elwidth != 1) newlsbp = new AstMul (nodep->fileline(), newlsbp,
+						    new AstConst (nodep->fileline(), elwidth));
 	    AstSel* newp = new AstSel (nodep->fileline(),
-				       fromp, newlsbp, widthp);
+				       fromp, newlsbp, newwidthp);
 	    newp->declRange(fromRange);
+	    newp->declElWidth(elwidth);
 	    UINFO(6,"   new "<<newp<<endl);
 	    if (debug()>=9) newp->dumpTree(cout,"--SELNEW: ");
 	    nodep->replaceWith(newp); pushDeletep(nodep); nodep=NULL;

test_regress/t/t_bitsel_slice.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_bitsel_slice.v

@@ -0,0 +1,82 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   logic [2:0] [1:0] in;
+   always @* in = crc[5:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   logic [1:0] [1:0]	out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out/*[1:0][1:0]*/),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in/*[2:0][1:0]*/));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {60'h0, out[1],out[0]};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hdc21e42d85441511
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   //bug717
+
+   input clk;
+   input logic [2:0][1:0] in;
+
+   output logic [1:0][1:0] out;
+
+   always @(posedge clk) begin
+      out <= in[2 -: 2];
+   end
+endmodule