diff --git a/test_regress/t/t_var_rsvd_bad.pl b/test_regress/t/t_var_rsvd_bad.pl
index a18f4edfa..75cc085d9 100755
--- a/test_regress/t/t_var_rsvd_bad.pl
+++ b/test_regress/t/t_var_rsvd_bad.pl
@@ -7,11 +7,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 
+top_filename("t/t_var_rsvd_port.v");
+
 compile (
 	 fails=>$Self->{v3},
 	 expect=>
-q{%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ common word: 'bool'
-%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ reserved word: 'switch'
+q{%Error-SYMRSVDWORD: t/t_var_rsvd_port.v:\d+: Symbol matches C\+\+ common word: 'bool'
+%Error-SYMRSVDWORD: t/t_var_rsvd_port.v:\d+: Symbol matches C\+\+ reserved word: 'switch'
 %Error: Exiting due to.*},
 	 );
 
diff --git a/test_regress/t/t_var_rsvd_port.pl b/test_regress/t/t_var_rsvd_port.pl
new file mode 100755
index 000000000..187aefc1a
--- /dev/null
+++ b/test_regress/t/t_var_rsvd_port.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 verilator_flags2=>["-Wno-SYMRSVDWORD"],
+	 );
+
+execute();
+
+ok(1);
+1;
diff --git a/test_regress/t/t_var_rsvd_bad.v b/test_regress/t/t_var_rsvd_port.v
similarity index 80%
rename from test_regress/t/t_var_rsvd_bad.v
rename to test_regress/t/t_var_rsvd_port.v
index 48492614b..63029b5f0 100644
--- a/test_regress/t/t_var_rsvd_bad.v
+++ b/test_regress/t/t_var_rsvd_port.v
@@ -13,6 +13,8 @@ module t (/*AUTOARG*/
    reg  vector;	// OK, as not public
    reg  switch /*verilator public*/;	// Bad
 
-   initial $stop;
-
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
 endmodule