diff --git a/Changes b/Changes
index 27e95dc8f..a5d688d56 100644
--- a/Changes
+++ b/Changes
@@ -19,6 +19,7 @@ Verilator 4.203 devel
 * Fix initialization of assoc in assoc array (#2914). [myftptoyman]
 * Fix merging of assignments in C++ code (#2970). [Ruper Swarbrick]
 * Fix --protect-ids when using SV classes (#2994). [Geza Lore]
+* Fix constant function calls with uninit value (#2995). [yanx21]
 
 
 Verilator 4.202 2021-04-24
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 02e6692cc..b992f9292 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -979,6 +979,17 @@ private:
         }
         SimStackNode stackNode(nodep, &tconnects);
         m_callStack.push_front(&stackNode);
+        // Clear output variable
+        if (auto* const basicp = VN_CAST(funcp->fvarp(), Var)->basicp()) {
+            AstConst cnst(funcp->fvarp()->fileline(), AstConst::WidthedValue(), basicp->widthMin(),
+                          0);
+            if (basicp->isZeroInit()) {
+                cnst.num().setAllBits0();
+            } else {
+                cnst.num().setAllBitsX();
+            }
+            newValue(funcp->fvarp(), &cnst);
+        }
         // Evaluate the function
         iterate(funcp);
         m_callStack.pop_front();
diff --git a/test_regress/t/t_func_uninit.pl b/test_regress/t/t_func_uninit.pl
new file mode 100755
index 000000000..2cb5eeaff
--- /dev/null
+++ b/test_regress/t/t_func_uninit.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_func_uninit.v b/test_regress/t/t_func_uninit.v
new file mode 100644
index 000000000..c9eb85468
--- /dev/null
+++ b/test_regress/t/t_func_uninit.v
@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+function int zeroed;
+endfunction
+
+function automatic integer what_bit;
+   input [31:0] a;
+   // what_bit = 0;
+   for (int i = 31; i >= 0; i = i - 1) begin
+      if (a[i] == 1'b1) begin
+         what_bit = i;
+      end
+   end
+endfunction
+
+module t(/*AUTOARG*/);
+
+   parameter ZERO = zeroed();
+
+   parameter PP = what_bit(0);
+
+   initial begin
+      if (ZERO != 0) $stop;
+      if (PP != 'x) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule