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Fix casting non-self-determined subexpressions (#2493).

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Wilson Snyder 2020-08-09 20:59:06 -04:00
parent 74754d94c3
commit 20c906261b
4 changed files with 65 additions and 2 deletions
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@ -12,6 +12,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix non-32 bit conversion to float (#2495). [dsvf]
**** Fix casting non-self-determined subexpressions (#2493). [phantom-killua]
* Verilator 4.038 2020-07-11

9
src/V3Width.cpp
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@ -1531,7 +1531,8 @@ private:
virtual void visit(AstCast* nodep) VL_OVERRIDE {
nodep->dtypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
// if (debug()) nodep->dumpTree(cout, " CastPre: ");
userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
userIterateAndNext(nodep->lhsp(), WidthVP(SELF, PRELIM).p());
// When more general casts are supported, the cast elimination will be done later.
// For now, replace it ASAP, so widthing can propagate easily
// The cast may change signing, but we don't know the sign yet. Make it so.
@ -1544,7 +1545,11 @@ private:
// Note widthCheckSized might modify nodep->lhsp()
AstNodeDType* subDTypep = nodep->findLogicDType(nodep->width(), nodep->width(),
nodep->lhsp()->dtypep()->numeric());
widthCheckSized(nodep, "Cast", nodep->lhsp(), subDTypep, EXTEND_EXP, false);
iterateCheck(nodep, "value", nodep->lhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP,
false);
} else {
iterateCheck(nodep, "value", nodep->lhsp(), SELF, FINAL, nodep->lhsp()->dtypep(),
EXTEND_EXP, false);
}
AstNode* newp = nodep->lhsp()->unlinkFrBack();
if (basicp->isDouble() && !newp->isDouble()) {

19
test_regress/t/t_math_shift_extend.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute();
ok(1);
1;

37
test_regress/t/t_math_shift_extend.v Normal file
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@ -0,0 +1,37 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
logic in1 = 1;
logic [1:0] in2 = 2'b11;
logic [31:0] out;
typedef logic [7:0] data_t;
// verilator lint_off WIDTH
initial begin
in1 = 1;
in2 = 0;
out = data_t'(in1 << in2);
if (out != 8'b1) $stop;
in2 = 1;
out = data_t'(in1 << in2);
if (out != 8'b10) $stop;
in2 = 2;
out = data_t'(in1 << in2);
if (out != 8'b100) $stop;
in2 = 3;
out = data_t'(in1 << in2);
if (out != 8'b1000) $stop;
$write("*-* All Finished *-*\n");
$finish();
end
endmodule