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Support "'dx" constants, bug1423.

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This commit is contained in:
Wilson Snyder 2019-05-01 20:02:28 -04:00
parent 9583f0d3cc
commit 1ff55c20e0
4 changed files with 53 additions and 12 deletions
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2
Changes
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@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Support '#' comments in $readmem, bug1411. [Frederick Requin]
**** Support "'dx" constants, bug1423. [Udi Finkelstein]
**** Add error when use parameters without value, bug1424. [Peter Gerst]
**** Fix missing VL_SHIFTL_ errors, bug1412, bug1415. [Larry Lee]

22
src/V3Number.cpp
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@ -153,18 +153,16 @@ V3Number::V3Number(FileLine* fileline, const char* sourcep) {
got_01 = 1;
break;
}
case 'z': case '?': {
if (!m_sized) m_fileline->v3error("Unsized X/Z/? not legal in decimal constant: "<<*cp);
setAllBitsZ();
got_z = 1;
break;
}
case 'x': {
if (!m_sized) m_fileline->v3error("Unsized X/Z/? not legal in decimal constant: "<<*cp);
got_x = 1;
setAllBitsX();
break;
}
case 'z': case '?': {
got_z = 1;
setAllBitsZ();
break;
}
case 'x': {
got_x = 1;
setAllBitsX();
break;
}
case '_': break;
default: {
m_fileline->v3error("Illegal character in decimal constant: "<<*cp);

20
test_regress/t/t_const.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2004 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

21
test_regress/t/t_const.v Normal file
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@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/);
initial begin
// verilator lint_off WIDTH
if (32'hxxxxxxxx !== 'hx) $stop;
if (32'hzzzzzzzz !== 'hz) $stop;
if (32'h???????? !== 'h?) $stop;
if (32'hxxxxxxxx !== 'dx) $stop;
if (32'hzzzzzzzz !== 'dz) $stop;
if (32'h???????? !== 'd?) $stop;
// verilator lint_on WIDTH
$write("*-* All Finished *-*\n");
$finish;
end
endmodule