forked from github/verilator
Tests: Clocking test to consider bug623.
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cce55941d3
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1fb2762725
@ -21,9 +21,8 @@ double sc_time_stamp () {
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VM_PREFIX* topp = NULL;
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VM_PREFIX* topp = NULL;
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void clockit(int clk1, int clk0) {
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void clockit(int clk1, int clk0) {
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#ifdef T_CLK_2IN_VEC
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topp->clks = clk1<<1 | clk0;
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topp->clks = clk1<<1 | clk0;
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#else
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#ifndef T_CLK_2IN_VEC
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topp->c1 = clk1;
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topp->c1 = clk1;
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topp->c0 = clk0;
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topp->c0 = clk0;
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#endif
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#endif
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@ -38,6 +37,7 @@ int main (int argc, char *argv[]) {
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topp = new VM_PREFIX;
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topp = new VM_PREFIX;
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topp->check = 0;
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topp->check = 0;
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clockit(0,0);
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clockit(0,0);
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main_time+=10;
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Verilated::debug(0);
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Verilated::debug(0);
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@ -49,6 +49,9 @@ int main (int argc, char *argv[]) {
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clockit(1, 1);
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clockit(1, 1);
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clockit(1, 0);
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clockit(1, 0);
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clockit(0, 0);
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clockit(0, 0);
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clockit(0, 1);
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clockit(1, 0);
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clockit(0, 0);
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}
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}
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topp->check = 1;
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topp->check = 1;
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clockit(0,0);
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clockit(0,0);
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@ -7,18 +7,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# Version 2.0.
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$Self->{vlt} or $Self->skip("Verilator only test");
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compile (
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compile (
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make_top_shell => 0,
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make_top_shell => 0,
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make_main => 0,
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make_main => 0,
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v_flags2 => ["$Self->{t_dir}/$Self->{name}.cpp"],
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verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"],
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verilator_flags2 => ["--exe"],
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vcs_flags2 => ['-assert'],
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);
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);
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execute (
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execute (
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check_finished=>1,
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check_finished=>1,
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);
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);
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ok(1);
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ok(1);
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1;
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1;
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@ -3,19 +3,75 @@
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// This file ONLY is placed into the Public Domain, for any use,
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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// without warranty, 2010 by Wilson Snyder.
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module t (
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`ifndef VERILATOR
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`ifdef T_CLK_2IN_VEC
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module t;
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input [1:0] clks,
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/*AUTOREGINPUT*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg c0; // To t2 of t2.v
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reg c1; // To t2 of t2.v
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reg check; // To t2 of t2.v
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reg [1:0] clks; // To t2 of t2.v
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// End of automatics
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t2 t2 (/*AUTOINST*/
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// Inputs
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.clks (clks[1:0]),
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.c0 (c0),
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.c1 (c1),
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.check (check));
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task clockit (input v1, v0);
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c1 = v1;
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c0 = v0;
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clks[1] = v1;
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clks[0] = v0;
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`ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif
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#1;
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endtask
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initial begin
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check = '0;
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c0 = '0;
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c1 = '0;
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clks = '0;
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#1
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t2.clear();
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#10;
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for (int i=0; i<2; i++) begin
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clockit(0, 0);
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clockit(0, 0);
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clockit(0, 1);
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clockit(1, 1);
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clockit(0, 0);
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clockit(1, 1);
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clockit(1, 0);
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clockit(0, 0);
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clockit(1, 0);
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clockit(0, 1);
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clockit(0, 0);
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end
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check = 1;
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clockit(0, 0);
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end
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endmodule
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`endif
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`ifdef VERILATOR
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`define t2 t
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`else
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`else
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`define t2 t2
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`endif
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module `t2 (
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input [1:0] clks,
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input c0,
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input c0,
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input c1,
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input c1,
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`endif
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input check
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input check
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);
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);
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`ifdef T_CLK_2IN_VEC
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`ifdef T_CLK_2IN_VEC
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wire c0 = clks[0];
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wire clk0 = clks[0];
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wire c1 = clks[1];
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wire clk1 = clks[1];
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`else
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wire clk0 = c0;
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wire clk1 = c1;
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`endif
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`endif
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integer p0 = 0;
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integer p0 = 0;
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@ -24,46 +80,82 @@ module t (
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integer n0 = 0;
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integer n0 = 0;
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integer n1 = 0;
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integer n1 = 0;
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integer n01 = 0;
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integer n01 = 0;
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integer vp = 0;
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integer vn = 0;
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integer vpn = 0;
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task clear;
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`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif
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p0 = 0;
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p1 = 0;
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p01 = 0;
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n0 = 0;
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n1 = 0;
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n01 = 0;
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vp = 0;
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vn = 0;
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vpn = 0;
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endtask
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`define display_counts(text) begin \
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`define display_counts(text) begin \
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$write("[%0t] ",$time); \
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$write("[%0t] ",$time); \
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`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
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`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
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$write(text); \
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$write(text); \
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$write(": %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01); \
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$write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \
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end
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end
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always @ (posedge c0) begin
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always @ (posedge clk0) begin
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p0 = p0 + 1; // Want blocking, so don't miss clock counts
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p0 = p0 + 1; // Want blocking, so don't miss clock counts
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`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif
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`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif
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end
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end
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always @ (posedge c1) begin
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always @ (posedge clk1) begin
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p1 = p1 + 1;
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p1 = p1 + 1;
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`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif
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`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif
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end
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end
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always @ (posedge c0 or posedge c1) begin
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always @ (posedge clk0 or posedge clk1) begin
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p01 = p01 + 1;
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p01 = p01 + 1;
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`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif
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`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif
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end
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end
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always @ (negedge c0) begin
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always @ (negedge clk0) begin
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n0 = n0 + 1;
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n0 = n0 + 1;
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`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif
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`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif
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end
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end
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always @ (negedge c1) begin
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always @ (negedge clk1) begin
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n1 = n1 + 1;
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n1 = n1 + 1;
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`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif
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`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif
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end
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end
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always @ (negedge c0 or negedge c1) begin
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always @ (negedge clk0 or negedge clk1) begin
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n01 = n01 + 1;
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n01 = n01 + 1;
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`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif
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`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif
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end
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end
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`ifndef VERILATOR
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always @ (posedge clks) begin
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vp = vp + 1;
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`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif
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end
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always @ (negedge clks) begin
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vn = vn + 1;
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`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif
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end
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always @ (posedge clks or negedge clks) begin
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vpn = vpn + 1;
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`ifdef TEST_VERBOSE `display_counts("or vec"); `endif
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end
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`endif
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always @ (posedge check) begin
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always @ (posedge check) begin
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if (p0!=4) $stop;
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if (p0!=6) $stop;
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if (p1!=4) $stop;
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if (p1!=6) $stop;
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if (p01!=6) $stop;
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if (p01!=10) $stop;
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if (n0!=4) $stop;
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if (n0!=6) $stop;
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if (n1!=4) $stop;
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if (n1!=6) $stop;
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if (n01!=6) $stop;
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if (n01!=10) $stop;
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`ifndef VERILATOR
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if (vp!=6) $stop;
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if (vn!=6) $stop;
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if (vpn!=12) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$write("*-* All Finished *-*\n");
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end
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end
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@ -9,13 +9,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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top_filename("t/t_clk_2in.v");
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top_filename("t/t_clk_2in.v");
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$Self->{vlt} or $Self->skip("Verilator only test");
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compile (
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compile (
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make_top_shell => 0,
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make_top_shell => 0,
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make_main => 0,
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make_main => 0,
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v_flags2 => ["+define+T_CLK_2IN_VEC=1 $Self->{t_dir}/t_clk_2in.cpp"],
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v_flags2 => ["+define+T_CLK_2IN_VEC=1"],
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verilator_flags2 => ["--exe"],
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verilator_flags2 => ["--exe $Self->{t_dir}/t_clk_2in.cpp"],
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);
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);
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execute (
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execute (
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