Parse event 'iff', still unsupported.

src/verilog.y

@@ -3302,8 +3302,11 @@ event_expression<senItemp>:     // IEEE: event_expression - split over several
 
 senitem<senItemp>:              // IEEE: part of event_expression, non-'OR' ',' terms
                 senitemEdge                             { $$ = $1; }
-        |       expr                                    { $$ = new AstSenItem{$<fl>1, VEdgeType::ET_CHANGED, $1}; }
+        |       expr
-        //UNSUP expr yIFF expr                          { UNSUP }
+                        { $$ = new AstSenItem{$<fl>1, VEdgeType::ET_CHANGED, $1}; }
+        |       expr yIFF expr
+                        { $$ = new AstSenItem{$<fl>1, VEdgeType::ET_CHANGED, $1};
+                          if ($2) BBUNSUP($2, "Unsupported: event expression 'iff'"); }
         ;
 
 senitemVar<senItemp>:
@@ -3311,12 +3314,21 @@ senitemVar<senItemp>:
         ;
 
 senitemEdge<senItemp>:          // IEEE: part of event_expression
-                yPOSEDGE expr                           { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2}; }
+                yPOSEDGE expr
-        |       yNEGEDGE expr                           { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2}; }
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2}; }
-        |       yEDGE expr                              { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2}; }
+        |       yNEGEDGE expr
-        //UNSUP yPOSEDGE expr yIFF expr                 { UNSUP }
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2}; }
-        //UNSUP yNEGEDGE expr yIFF expr                 { UNSUP }
+        |       yEDGE expr
-        //UNSUP yEDGE expr yIFF expr                    { UNSUP }
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2}; }
+        |       yPOSEDGE expr yIFF expr
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2};
+                          BBUNSUP($3, "Unsupported: event expression 'iff'"); }
+        |       yNEGEDGE expr yIFF expr
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2};
+                          BBUNSUP($3, "Unsupported: event expression 'iff'"); }
+        |       yEDGE expr yIFF expr
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2};
+                          BBUNSUP($3, "Unsupported: event expression 'iff'"); }
         ;
 
 //************************************************

test_regress/t/t_iff.out

@@ -1,7 +1,17 @@
-%Error: t/t_iff.v:64:15: syntax error, unexpected iff, expecting ')' or ',' or or
+%Error-UNSUPPORTED: t/t_iff.v:66:15: Unsupported: event expression 'iff'
-   64 |    always @(d iff enable == 1) begin
+   66 |    always @(d iff enable) begin
       |               ^~~
-%Error: t/t_iff.v:69:35: syntax error, unexpected iff, expecting ')'
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-   69 |    assert property (@(posedge clk iff enable)
+%Error-UNSUPPORTED: t/t_iff.v:71:23: Unsupported: event expression 'iff'
+   71 |    always @(posedge d iff enable) begin
+      |                       ^~~
+%Error-UNSUPPORTED: t/t_iff.v:76:23: Unsupported: event expression 'iff'
+   76 |    always @(negedge d iff enable) begin
+      |                       ^~~
+%Error-UNSUPPORTED: t/t_iff.v:81:20: Unsupported: event expression 'iff'
+   81 |    always @(edge d iff enable) begin
+      |                    ^~~
+%Error-UNSUPPORTED: t/t_iff.v:86:35: Unsupported: event expression 'iff'
+   86 |    assert property (@(posedge clk iff enable)
       |                                   ^~~
 %Error: Exiting due to

test_regress/t/t_iff.pl

@@ -11,6 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
+    verilator_flags2 => ['--timing'],
     fails => $Self->{vlt_all},  # Verilator unsupported, bug1482, iff not supported
     expect_filename => $Self->{golden_filename},
     );

test_regress/t/t_iff.v

@@ -42,7 +42,7 @@ module t (/*AUTOARG*/
          $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
          if (crc !== 64'hc77bb9b3784ea091) $stop;
          // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'he58508de5310b541
+`define EXPECTED_SUM 64'h390aa8652d33a691
          if (sum !== `EXPECTED_SUM) $stop;
          $write("*-* All Finished *-*\n");
          $finish;
@@ -59,10 +59,27 @@ module Test
    output wire [31:0] result);
 
    wire         enable = crc[32];
-   wire [31:0]  d = crc[31:0];
+   wire [7:0]  d = crc[7:0];
-   logic [31:0] y;
+
-   always @(d iff enable == 1) begin
+
-      y <= d;
+   logic [7:0] d0_r;
+   always @(d iff enable) begin
+      d0_r <= d;
+   end
+
+   logic [7:0] d1_r;
+   always @(posedge d iff enable) begin
+      d1_r <= d;
+   end
+
+   logic [7:0] d2_r;
+   always @(negedge d iff enable) begin
+      d2_r <= d;
+   end
+
+   logic [7:0] d3_r;
+   always @(edge d iff enable) begin
+      d3_r <= d;
    end
 
    wire reset = (cyc < 10);
@@ -71,6 +88,6 @@ module Test
                     (crc != '0));
 
    // Aggregate outputs into a single result vector
-   assign result = {32'h0, y};
+   assign result = {32'h0, d3_r, d2_r, d1_r, d0_r};
 
 endmodule

test_regress/t/t_wait_order.out

@@ -2,19 +2,16 @@
    16 |       wait_order (a, b) wif[0] = '1;
       |                       ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_wait_order.v:19:23: Unsupported: wait_order
+%Error-UNSUPPORTED: t/t_wait_order.v:25:23: Unsupported: wait_order
-   19 |       wait_order (b, a) nif[0] = '1;
+   25 |       wait_order (a, b) else welse[1] = '1;
       |                       ^
-%Error-UNSUPPORTED: t/t_wait_order.v:23:23: Unsupported: wait_order
+%Error-UNSUPPORTED: t/t_wait_order.v:28:23: Unsupported: wait_order
-   23 |       wait_order (a, b) else welse[1] = '1;
+   28 |       wait_order (b, a) else nelse[1] = '1;
       |                       ^
-%Error-UNSUPPORTED: t/t_wait_order.v:26:23: Unsupported: wait_order
+%Error-UNSUPPORTED: t/t_wait_order.v:32:23: Unsupported: wait_order
-   26 |       wait_order (b, a) else nelse[1] = '1;
+   32 |       wait_order (a, b) wif[2] = '1; else welse[2] = '1;
       |                       ^
-%Error-UNSUPPORTED: t/t_wait_order.v:30:23: Unsupported: wait_order
+%Error-UNSUPPORTED: t/t_wait_order.v:35:23: Unsupported: wait_order
-   30 |       wait_order (a, b) wif[2] = '1; else welse[2] = '1;
+   35 |       wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
-      |                       ^
-%Error-UNSUPPORTED: t/t_wait_order.v:33:23: Unsupported: wait_order
-   33 |       wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
       |                       ^
 %Error: Exiting due to

test_regress/t/t_wait_order.v

@@ -15,9 +15,11 @@ module t(/*AUTOARG*/);
    initial begin
       wait_order (a, b) wif[0] = '1;
    end
+`ifdef FAIL_ASSERT_1
    initial begin
       wait_order (b, a) nif[0] = '1;
    end
+`endif
 
    initial begin
       wait_order (a, b) else welse[1] = '1;
@@ -41,7 +43,7 @@ module t(/*AUTOARG*/);
       #10;
       -> c;
       #10;
-      // NOTE This hasn't been validated against other simulators
+
       `checkd(wif[0], 1'b1);
       `checkd(nif[0], 1'b0);