Add VL_TIME_MULTIPLIER to allow sub-timeunit time printing

include/verilated.cpp

@@ -229,6 +229,22 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
 		    output += tmp;
 		    break;
 		}
+		case 't': { // Time
+		    int digits;
+		    if (VL_TIME_MULTIPLIER==1) {
+			digits=sprintf(tmp,"%llu",ld);
+		    } else if (VL_TIME_MULTIPLIER==1000) {
+			digits=sprintf(tmp,"%llu.%03llu",
+				       (QData)(ld/VL_TIME_MULTIPLIER),
+				       (QData)(ld%VL_TIME_MULTIPLIER));
+		    } else {
+			vl_fatal(__FILE__,__LINE__,"","%%Error: Unsupported VL_TIME_MULTIPLIER");
+		    }
+		    int needmore = width-digits;
+		    if (needmore>0) output.append(needmore,' '); // Pre-pad spaces
+		    output += tmp;
+		    break;
+		}
 		case 'b':
 		    for (; lsb>=0; lsb--) {
 			output += ((lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 1) + '0';
@@ -386,6 +402,7 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
 		    VL_SET_WQ(owp,ld);
 		    break;
 		}
+		case 't': // FALLTHRU  // Time
 		case 'u': { // Unsigned decimal
 		    _vl_vsss_skipspace(fp,floc,fromp);
 		    _vl_vsss_read(fp,floc,fromp, tmp, "0123456789+-xz?_");

include/verilated.h

@@ -255,13 +255,17 @@ static inline void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp) {
 //=========================================================================
 // Pli macros
 
+#ifndef VL_TIME_MULTIPLIER
+# define VL_TIME_MULTIPLIER 1
+#endif
+
 /// Return current simulation time
 #if defined(SYSTEMC_VERSION) && (SYSTEMC_VERSION>20011000)
-# define VL_TIME_I(ign) ((IData)sc_time_stamp().to_default_time_units())
+# define VL_TIME_I(ign) ((IData)(sc_time_stamp().to_default_time_units()*VL_TIME_MULTIPLIER))
-# define VL_TIME_Q(ign) ((QData)sc_time_stamp().to_default_time_units())
+# define VL_TIME_Q(ign) ((QData)(sc_time_stamp().to_default_time_units()*VL_TIME_MULTIPLIER))
 #else
-# define VL_TIME_I(ign) ((IData)sc_time_stamp())
+# define VL_TIME_I(ign) ((IData)(sc_time_stamp()*VL_TIME_MULTIPLIER))
-# define VL_TIME_Q(ign) ((QData)sc_time_stamp())
+# define VL_TIME_Q(ign) ((QData)(sc_time_stamp()*VL_TIME_MULTIPLIER))
 extern double sc_time_stamp();
 #endif
 

src/V3EmitC.cpp

@@ -1051,7 +1051,7 @@ void EmitCStmts::displayArg(AstNode* dispp, AstNode** elistp, bool isScan,
 
     //string pfmt = "%"+displayFormat(argp, vfmt, fmtLetter)+fmtLetter;
     string pfmt;
-    if ((fmtLetter=='u' || fmtLetter=='d')
+    if ((fmtLetter=='u' || fmtLetter=='d' || fmtLetter=='t')
 	&& !isScan
 	&& vfmt == "") { // Size decimal output.  Spec says leading spaces, not zeros
 	double mantissabits = argp->widthMin() - ((fmtLetter=='d')?1:0);
@@ -1105,7 +1105,7 @@ void EmitCStmts::displayNode(AstNode* nodep, const string& vformat, AstNode* exp
 	    // Spec: h d o b c l
 	    case 'b': displayArg(nodep,&elistp,isScan, vfmt,'b'); break;
 	    case 'c': displayArg(nodep,&elistp,isScan, vfmt,'c'); break;
-	    case 't':
+	    case 't': displayArg(nodep,&elistp,isScan, vfmt,'t'); break;
 	    case 'd': displayArg(nodep,&elistp,isScan, vfmt,'u'); break;  // Unsigned decimal
 	    case 'o': displayArg(nodep,&elistp,isScan, vfmt,'o'); break;
 	    case 'h':

src/V3Number.cpp

@@ -429,7 +429,7 @@ string V3Number::displayed(const string& vformat) const {
 	return str;
     }
     case '~': // Signed decimal
-    case 't':
+    case 't': // Time
     case 'd': { // Unsigned decimal
 	bool issigned = (code == '~');
 	if (fmtsize == "") {

test_regress/driver.pl

@@ -543,6 +543,10 @@ sub _make_main {
     my $filename = "obj_dir/$self->{VM_PREFIX}__main.cpp";
     my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,";
 
+    print $fh "// Test defines\n";
+    print $fh "#define VL_TIME_MULTIPLIER $self->{vl_time_multiplier}\n" if $self->{vl_time_multiplier};
+
+    print $fh "// Generated header\n";
     my $VM_PREFIX = $self->{VM_PREFIX};
     print $fh "#include \"$VM_PREFIX.h\"\n";
 

test_regress/t/t_display_time.pl

@@ -0,0 +1,31 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+$Last_Self->{vl_time_multiplier} = 1000;
+
+compile (
+    verilator_flags2 => ['-DVL_TIME_MULTIPLER=1000'],
+    );
+
+execute (
+	 check_finished=>1,
+	 expect=> quotemeta(
+'default:   [0.000] 0t time [               0.000] No0 time
+'
+# Unsupported:
+#'default:   [0] 0t time [                   0] No0 time
+#-9,0,,0:   [0] 0t time [0] No0 time
+#-9,0,,10:  [0] 0t time [         0] No0 time
+#-9,0,ns,5: [0ns] 0t time [  0ns] No0 time
+#-9,3,ns,8: [0.000ns] 0t time [ 0.000ns] No0 time
+#'
+),
+     );
+
+ok(1);
+1;

test_regress/t/t_display_time.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+
+`timescale 1ns/1ns
+
+module t;
+   initial begin
+      // Display formatting
+      $write("default:   [%0t] 0t time [%t] No0 time\n",$time,$time);
+`ifndef verilator // Unsupported
+      $timeformat(-9, 0, "",   0);
+      $write("-9,0,,0:   [%0t] 0t time [%t] No0 time\n",$time,$time);
+      $timeformat(-9, 0, "",   10);
+      $write("-9,0,,10:  [%0t] 0t time [%t] No0 time\n",$time,$time);
+      $timeformat(-9, 0, "ns", 5);
+      $write("-9,0,ns,5: [%0t] 0t time [%t] No0 time\n",$time,$time);
+      $timeformat(-9, 3, "ns", 8);
+      $write("-9,3,ns,8: [%0t] 0t time [%t] No0 time\n",$time,$time);
+`endif
+      $write("\n");
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule