forked from github/verilator
Fix output with select hitting tristate, bug514.
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6d0f39d841
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@ -1036,6 +1036,10 @@ class TristateVisitor : public TristateBaseVisitor {
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nodep->user2(U2_GRAPHING);
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AstVar* enModVarp = (AstVar*) nodep->modVarp()->user1p();
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if (!enModVarp) {
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if (nodep->exprp()) {
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// May have an output only that later connects to a tristate, so simplify now.
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V3Inst::pinReconnectSimple(nodep, m_cellp, m_modp, false);
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}
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iteratePinGuts(nodep);
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return; // No __en signals on this pin
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}
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15
test_regress/t/t_tri_graph.pl
Executable file
15
test_regress/t/t_tri_graph.pl
Executable file
@ -0,0 +1,15 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# Compile only test
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compile (
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);
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ok(1);
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1;
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27
test_regress/t/t_tri_graph.v
Normal file
27
test_regress/t/t_tri_graph.v
Normal file
@ -0,0 +1,27 @@
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// DESCRIPTION: Verilator: Unsupported tristate constructur error
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//
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// This is a compile only regression test of tristate handling for bug514
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [11:0] ck;
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assign ck[1:0] = {1'bz,{1{1'b0}}};
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test i_test (.clk (ck[1:0]));
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endmodule
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module test (clk);
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output wire [1:0] clk;
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endmodule // test
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