Fix output with select hitting tristate, bug514.

This commit is contained in:
Wilson Snyder 2012-05-15 19:26:20 -04:00
parent 6d0f39d841
commit 1b1991d53d
3 changed files with 46 additions and 0 deletions

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@ -1036,6 +1036,10 @@ class TristateVisitor : public TristateBaseVisitor {
nodep->user2(U2_GRAPHING);
AstVar* enModVarp = (AstVar*) nodep->modVarp()->user1p();
if (!enModVarp) {
if (nodep->exprp()) {
// May have an output only that later connects to a tristate, so simplify now.
V3Inst::pinReconnectSimple(nodep, m_cellp, m_modp, false);
}
iteratePinGuts(nodep);
return; // No __en signals on this pin
}

15
test_regress/t/t_tri_graph.pl Executable file
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@ -0,0 +1,15 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# Compile only test
compile (
);
ok(1);
1;

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@ -0,0 +1,27 @@
// DESCRIPTION: Verilator: Unsupported tristate constructur error
//
// This is a compile only regression test of tristate handling for bug514
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [11:0] ck;
assign ck[1:0] = {1'bz,{1{1'b0}}};
test i_test (.clk (ck[1:0]));
endmodule
module test (clk);
output wire [1:0] clk;
endmodule // test