diff --git a/src/verilog.y b/src/verilog.y index fbd35fd85..32967ac33 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1527,7 +1527,7 @@ assignOne: delayE: /* empty */ { } - | delay_control { $1->v3warn(ASSIGNDLY,"Ignoring delay on this assignment/primitive."); } /* ignored */ + | delay_control { $1->v3warn(ASSIGNDLY,"Unsupported: Ignoring delay on this assignment/primitive."); } /* ignored */ ; delay_control: //== IEEE: delay_control @@ -1929,7 +1929,7 @@ statement_item: // IEEE: statement_item // //UNSUP par_block { $$ = $1; } // // IEEE: procedural_timing_control_statement + procedural_timing_control - | delay_control stmtBlock { $$ = $2; $1->v3warn(STMTDLY,"Ignoring delay on this delayed statement."); } + | delay_control stmtBlock { $$ = $2; $1->v3warn(STMTDLY,"Unsupported: Ignoring delay on this delayed statement."); } //UNSUP event_control stmtBlock { UNSUP } //UNSUP cycle_delay stmtBlock { UNSUP } // diff --git a/test_regress/t/t_delay_stmtdly_bad.pl b/test_regress/t/t_delay_stmtdly_bad.pl index 730ce27fc..9e5bd4717 100755 --- a/test_regress/t/t_delay_stmtdly_bad.pl +++ b/test_regress/t/t_delay_stmtdly_bad.pl @@ -15,11 +15,11 @@ compile ( verilator_flags2 => ['-Wall -Wno-DECLFILENAME'], fails=>1, expect=> -'%Warning-ASSIGNDLY: t/t_delay.v:\d+: Ignoring delay on this assignment/primitive. +'%Warning-ASSIGNDLY: t/t_delay.v:\d+: Unsupported: Ignoring delay on this assignment/primitive. %Warning-ASSIGNDLY: Use .* -%Warning-ASSIGNDLY: t/t_delay.v:\d+: Ignoring delay on this assignment/primitive. -%Warning-ASSIGNDLY: t/t_delay.v:\d+: Ignoring delay on this assignment/primitive. -%Warning-STMTDLY: t/t_delay.v:\d+: Ignoring delay on this delayed statement. +%Warning-ASSIGNDLY: t/t_delay.v:\d+: Unsupported: Ignoring delay on this assignment/primitive. +%Warning-ASSIGNDLY: t/t_delay.v:\d+: Unsupported: Ignoring delay on this assignment/primitive. +%Warning-STMTDLY: t/t_delay.v:\d+: Unsupported: Ignoring delay on this delayed statement. .*%Error: Exiting due to.*', );