Fix error when dotted refers to missing module (#2095).

Changes

@@ -21,6 +21,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix genblk naming to match IEEE (#2686). [tinshark]
 
+****  Fix error when dotted refers to missing module (#2095). [Stefan Wallentowitz]
+
 
 * Verilator 4.106 2020-12-02
 

src/V3LinkDot.cpp

@@ -645,6 +645,10 @@ public:
                     if (AstNodeModule* modp = cellp->modp()) {
                         if (modp->hierBlock()) {
                             refLocationp->v3error("Cannot access inside hierarchical block");
+                        } else if (VN_IS(modp, NotFoundModule)) {
+                            refLocationp->v3error(
+                                "Dotted reference to cell that refers to missing module: "
+                                << modp->prettyNameQ());
                         }
                     }
                 }

test_regress/t/t_inst_missing_dot_bad.out

@@ -0,0 +1,7 @@
+%Error: t/t_inst_missing_dot_bad.v:9:22: Dotted reference to cell that refers to missing module: 'missing'
+    9 |       $display("a=", missing.a);
+      |                      ^~~~~~~
+%Error: t/t_inst_missing_dot_bad.v:9:30: Can't find definition of 'a' in dotted variable: 'missing.a'
+    9 |       $display("a=", missing.a);
+      |                              ^
+%Error: Exiting due to

test_regress/t/t_inst_missing_dot_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_missing_dot_bad.v

@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Stefan Wallentowitz.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   initial begin
+      $display("a=", missing.a);
+   end
+   missing missing();  // Intentionally missing
+endmodule