Support bind in , bug602.

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Support pattern assignment features, bug616, bug617, bug618. [Ed Lander]
 
+****  Support bind in $unit, bug602. [Ed Lander]
+
 ****  Fix DETECTARRAY on packed structures, bug610. [Jeremy Bennett]
 
 ****  Fix LITENDIAN on unpacked structures, bug614. [Wai Sum Mong]

src/verilog.y

@@ -651,7 +651,7 @@ description:			// ==IEEE: description
 	|	program_declaration			{ }
 	|	package_declaration			{ }
 	|	package_item				{ if ($1) GRAMMARP->unitPackage($1->fileline())->addStmtp($1); }
-	//UNSUP	bind_directive				{ }
+       	|	bind_directive				{ if ($1) GRAMMARP->unitPackage($1->fileline())->addStmtp($1); }
 	//	unsupported	// IEEE: config_declaration
 	//			// Verilator only
 	|	vltItem					{ }

test_regress/t/t_bind.v

@@ -3,7 +3,14 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2012 by Wilson Snyder.
 
-module t;
+bit a_finished;
+bit b_finished;
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
    wire [31:0] o;
    wire        si = 1'b0;
 
@@ -18,6 +25,13 @@ module t;
 	   // Inputs
 	   .si				(si));
 
+   always @ (posedge clk) begin
+      if (!a_finished) $stop;
+      if (!b_finished) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
 endmodule
 
 module InstModule (
@@ -28,10 +42,7 @@ module InstModule (
 endmodule
 
 program Prog (input si);
-   initial begin
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+   initial a_finished = 1'b1;
 endprogram
 
 module ExampInst (o,i);
@@ -55,3 +66,12 @@ module ExampInst (o,i);
 
 endmodule
 
+// Check bind at top level
+bind InstModule Prog2 instProg2
+  (/*AUTOBIND*/
+   .si      (si));
+
+// Check program declared after bind
+program Prog2 (input si);
+   initial b_finished = 1'b1;
+endprogram