diff --git a/Changes b/Changes
index da21e4d4a..1970691f2 100644
--- a/Changes
+++ b/Changes
@@ -23,6 +23,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix realpath compile issue on MSVC++, bug1141. [Miodrag Milanovic]
 
+****  Fix missing error on interface size mismatch, bug1143.  [Johan Bjork]
+
 
 * Verilator 3.900 2017-01-15
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 446cb436c..5a91797b7 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2168,14 +2168,24 @@ private:
                 }
 
 		// TODO Simple dtype checking, should be a more general check
-		bool hiArray = exprDTypep->skipRefp()->castUnpackArrayDType();
-		bool loArray = modDTypep->skipRefp()->castUnpackArrayDType();
-		if (loArray != hiArray && pinwidth != conwidth) {
+		AstNodeArrayDType* loArrayp = exprDTypep->skipRefp()->castUnpackArrayDType();
+		AstNodeArrayDType* hiArrayp = modDTypep->skipRefp()->castUnpackArrayDType();
+		if (loArrayp && hiArrayp && loArrayp->subDTypep()->skipRefp()->castIfaceRefDType() 
+		    && loArrayp->declRange().elements() != hiArrayp->declRange().elements()) {
+		    int loSize = loArrayp->declRange().elements();
+		    int hiSize = hiArrayp->declRange().elements();
 		    nodep->v3error("Illegal "<<nodep->prettyOperatorName()<<","
-				   <<" mismatch between port which is"<<(hiArray?"":" not")<<" an array,"
-				   <<" and expression which is"<<(loArray?"":" not")<<" an array.");
-		    UINFO(1,"    Related lo: "<<exprDTypep->skipRefp()<<endl);
-		    UINFO(1,"    Related hi: "<<modDTypep->skipRefp()<<endl);
+				   <<" mismatch between port which is an interface array of size "<<loSize<<","
+				   <<" and expression which is an interface array of size "<<hiSize<<".");
+		    UINFO(1,"    Related lo: "<<modDTypep->skipRefp()<<endl);
+		    UINFO(1,"    Related hi: "<<exprDTypep->skipRefp()<<endl);
+		} else if ((loArrayp && !hiArrayp && pinwidth != conwidth)
+			   || (!loArrayp && hiArrayp && pinwidth != conwidth)) {
+		    nodep->v3error("Illegal "<<nodep->prettyOperatorName()<<","
+				   <<" mismatch between port which is"<<(loArrayp?"":" not")<<" an array,"
+				   <<" and expression which is"<<(hiArrayp?"":" not")<<" an array.");
+		    UINFO(1,"    Related lo: "<<modDTypep->skipRefp()<<endl);
+		    UINFO(1,"    Related hi: "<<exprDTypep->skipRefp()<<endl);
 		}
 		iterateCheckAssign(nodep,"pin connection",nodep->exprp(),FINAL,subDTypep);
 	    }
diff --git a/test_regress/t/t_interface_size_bad.pl b/test_regress/t/t_interface_size_bad.pl
new file mode 100755
index 000000000..238429584
--- /dev/null
+++ b/test_regress/t/t_interface_size_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	fails=>1,
+	expect=>
+q{%Error: t/t_interface_size_bad.v:\d+: Illegal IFACEREF port connection 'foo', mismatch between port which is an interface array of size 4, and expression which is an interface array of size 5.
+%Error: t/t_interface_size_bad.v:\d+: Illegal IFACEREF port connection 'foo', mismatch between port which is an interface array of size 6, and expression which is an interface array of size 5.
+%Error: Exiting due to.*},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_size_bad.v b/test_regress/t/t_interface_size_bad.v
new file mode 100644
index 000000000..4066254a8
--- /dev/null
+++ b/test_regress/t/t_interface_size_bad.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Demonstrate deferred linking error messages
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Johan Bjork.
+
+interface foo_intf;
+   logic a;
+endinterface
+
+module t (/*AUTOARG*/);
+   localparam N = 4;
+   foo_intf foo4 [N-1:0] ();
+   foo_intf foo6 [5:0] ();
+
+   baz baz4_inst (.foo(foo4));
+   baz baz6_inst (.foo(foo6));
+
+endmodule
+
+module baz(foo_intf foo[4:0] );
+endmodule