diff --git a/Changes b/Changes index b43f2fa0c..52b74c8fb 100644 --- a/Changes +++ b/Changes @@ -25,6 +25,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix mis-optimizing public DPI functions, bug963. [Wei Song] +**** Fix package:scope.scope variable references. + * Verilator 3.876 2015-08-12 diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index b1d36ebfc..686958b65 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -1491,7 +1491,7 @@ private: if (nodep->user3SetOnce()) return; UINFO(8," "<=9) nodep->dumpTree("-dot-in: "); @@ -1502,7 +1502,7 @@ private: // m_ds.m_dotText communicates the cell prefix between stages if (nodep->lhsp()->castPackageRef()) { - if (!start) { nodep->lhsp()->v3error("Package reference may not be embedded in dotted reference"); m_ds.m_dotErr=true; } + //if (!start) { nodep->lhsp()->v3error("Package reference may not be embedded in dotted reference"); m_ds.m_dotErr=true; } m_ds.m_dotPos = DP_PACKAGE; } else { m_ds.m_dotPos = DP_SCOPE; @@ -1552,7 +1552,7 @@ private: if (!m_ds.m_dotSymp) nodep->v3fatalSrc("NULL lookup symbol table"); if (!m_statep->forPrimary()) nodep->v3fatalSrc("ParseRefs should no longer exist"); DotStates lastStates = m_ds; - bool start = !m_ds.m_dotp; + bool start = (m_ds.m_dotPos == DP_NONE); // Save, as m_dotp will be changed if (start) { m_ds.init(m_curSymp); // Note m_ds.m_dot remains NULL; this is a reference not under a dot diff --git a/test_regress/t/t_package_dot.pl b/test_regress/t/t_package_dot.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_package_dot.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_package_dot.v b/test_regress/t/t_package_dot.v new file mode 100644 index 000000000..b848b228e --- /dev/null +++ b/test_regress/t/t_package_dot.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +package pkg; + typedef struct packed { + logic [3:0] msk; + logic [3:0] dat; + } STR_t; +endpackage; + +package csr_pkg; + typedef pkg::STR_t reg_t; + localparam reg_t REG_RST = 8'h34; +endpackage + +module t (/*AUTOARG*/); + initial begin + if (csr_pkg::REG_RST.msk != 4'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule