forked from github/verilator
Fix logical not optimization with empty begin, #2291.
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@ -38,6 +38,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix error on unpacked connecting to packed, #2288. [Joseph Shaker]
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**** Fix logical not optimization with empty begin, #2291. [Baltazar Ortiz]
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* Verilator 4.032 2020-04-04
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@ -1954,7 +1954,8 @@ private:
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|| VN_IS(nodep->condp(), LogNot))
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&& nodep->ifsp() && nodep->elsesp()) {
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UINFO(4, "IF(NOT {x}) => IF(x) swapped if/else" << nodep << endl);
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AstNode* condp = VN_CAST(nodep->condp(), Not)->lhsp()->unlinkFrBackWithNext();
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AstNode* condp
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= VN_CAST(nodep->condp(), NodeUniop)->lhsp()->unlinkFrBackWithNext();
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AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();
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AstNode* elsesp = nodep->elsesp()->unlinkFrBackWithNext();
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AstIf* ifp = new AstIf(nodep->fileline(), condp, elsesp, ifsp);
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17
test_regress/t/t_if_swap.pl
Executable file
17
test_regress/t/t_if_swap.pl
Executable file
@ -0,0 +1,17 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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ok(1);
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1;
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24
test_regress/t/t_if_swap.v
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24
test_regress/t/t_if_swap.v
Normal file
@ -0,0 +1,24 @@
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module t
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(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer f;
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always @(posedge clk) begin
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if (!$feof(f)) begin
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$display("Doing stuff with file.");
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end
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// Commenting out these two lines fixes the fault
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else begin
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end
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if (!$feof(f)) begin
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end
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else begin
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$display("Not doing stuff with file.");
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end
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end
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endmodule
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