From 14f58ed6c7c552dd5a89856660f71c22c82ddafb Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 15 Oct 2022 06:21:34 -0400
Subject: [PATCH] Add error on real edge event control.

---
 Changes                             |  1 +
 src/V3Ast.h                         |  1 +
 src/V3Width.cpp                     |  4 ++++
 test_regress/t/t_lint_edge_real.out |  5 +++++
 test_regress/t/t_lint_edge_real.pl  | 19 +++++++++++++++++++
 test_regress/t/t_lint_edge_real.v   | 18 ++++++++++++++++++
 6 files changed, 48 insertions(+)
 create mode 100644 test_regress/t/t_lint_edge_real.out
 create mode 100755 test_regress/t/t_lint_edge_real.pl
 create mode 100644 test_regress/t/t_lint_edge_real.v

diff --git a/Changes b/Changes
index bdb6af7f9..7a1acb363 100644
--- a/Changes
+++ b/Changes
@@ -40,6 +40,7 @@ Verilator 4.228 2022-10-01
 * Add --build-jobs, and rework arguments for -j (#3623). [Kamil Rakoczy]
 * Rename --bin to --build-dep-bin.
 * Rename debug flags --dumpi-tree, --dumpi-graph, etc. [Geza Lore]
+* Add error on real edge event control.
 * Fix thread saftey in SystemC VL_ASSIGN_SBW/WSB (#3494) (#3513). [Mladen Slijepcevic]
 * Fix crash in gate optimization of circular logic (#3543). [Bill Flynn]
 * Fix arguments in non-static method call (#3547) (#3582). [Gustav Svensk]
diff --git a/src/V3Ast.h b/src/V3Ast.h
index fa33caca9..dccd8ddc5 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -297,6 +297,7 @@ public:
         };
         return clocked[m_e];
     }
+    bool anEdge() const { return m_e == ET_BOTHEDGE || m_e == ET_POSEDGE || m_e == ET_NEGEDGE; }
     VEdgeType invert() const {
         switch (m_e) {
         case ET_CHANGED: return ET_CHANGED;
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index ffb9e8d08..a2ec63a30 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -5131,6 +5131,10 @@ private:
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else {
             userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+            if (nodep->edgeType().anEdge() && nodep->sensp()->dtypep()->skipRefp()->isDouble()) {
+                nodep->sensp()->v3error(
+                    "Edge event control not legal on real type (IEEE 1800-2017 6.12.1)");
+            }
         }
     }
     void visit(AstWait* nodep) override {
diff --git a/test_regress/t/t_lint_edge_real.out b/test_regress/t/t_lint_edge_real.out
new file mode 100644
index 000000000..bc9f0f0d5
--- /dev/null
+++ b/test_regress/t/t_lint_edge_real.out
@@ -0,0 +1,5 @@
+%Error: t/t_lint_edge_real.v:16:22: Edge event control not legal on real type (IEEE 1800-2017 6.12.1)
+                                  : ... In instance t
+   16 |    always @ (posedge rbad) $stop;
+      |                      ^~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_lint_edge_real.pl b/test_regress/t/t_lint_edge_real.pl
new file mode 100755
index 000000000..07964a1b5
--- /dev/null
+++ b/test_regress/t/t_lint_edge_real.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_edge_real.v b/test_regress/t/t_lint_edge_real.v
new file mode 100644
index 000000000..58dfad8ad
--- /dev/null
+++ b/test_regress/t/t_lint_edge_real.v
@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   rbad, rok
+   );
+   input real rbad;
+   input real rok;
+
+   always @ (rok) $stop;
+
+   always @ (posedge rbad) $stop;
+
+endmodule