forked from github/verilator
parent
c61258c0d0
commit
14d24213a8
@ -111,6 +111,7 @@ Vassilis Papaefstathiou
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Veripool API Bot
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Veripool API Bot
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Victor Besyakov
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Victor Besyakov
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Wilson Snyder
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Wilson Snyder
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Xi Zhang
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Yossi Nivin
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Yossi Nivin
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Yuri Victorovich
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Yuri Victorovich
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Yutetsu TAKATSUKASA
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Yutetsu TAKATSUKASA
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@ -475,6 +475,9 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read()
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# define VL_CPU_RELAX() asm volatile("yield" ::: "memory")
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# define VL_CPU_RELAX() asm volatile("yield" ::: "memory")
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# elif defined(__powerpc64__)
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# elif defined(__powerpc64__)
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# define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory")
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# define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory")
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# elif defined(__loongarch__)
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// LoongArch does not currently have a yield/pause instruction
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# define VL_CPU_RELAX() asm volatile("nop" ::: "memory")
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# else
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# else
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# error "Missing VL_CPU_RELAX() definition. Or, don't use VL_THREADED"
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# error "Missing VL_CPU_RELAX() definition. Or, don't use VL_THREADED"
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# endif
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# endif
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