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Remove mis-committed debug print

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Wilson Snyder 2008-09-22 20:10:10 -04:00
parent f197dd29cb
commit 11b9a631d4
1 changed files with 1 additions and 1 deletions
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src/verilog.y
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@ -1486,7 +1486,7 @@ pslDirOne<nodep>:
;
pslDecl<nodep>:
yDEFAULT yPSL_CLOCK '=' senitemEdge ';' { $$ = new AstPslDefClock($3, $4); UINFO(0,"CRE "<<$$<<endl)}
yDEFAULT yPSL_CLOCK '=' senitemEdge ';' { $$ = new AstPslDefClock($3, $4); }
| yDEFAULT yPSL_CLOCK '=' '(' senitemEdge ')' ';' { $$ = new AstPslDefClock($3, $5); }
;