Fix hang on concat error, bug1608.

Changes

@@ -18,6 +18,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix for loop missing initializer, bug1605. [Andrew Holme]
 
+****  Fix hang on concat error, bug1608. [Bogdan Vukobratovic]
+
 
 * Verilator 4.022 2019-11-10
 

src/V3LinkDot.cpp

@@ -1954,7 +1954,8 @@ private:
             AstNode* varEtcp = m_ds.m_dotp->lhsp()->unlinkFrBack();
             AstNode* newp = new AstMemberSel(nodep->fileline(), varEtcp,
                                              VFlagChildDType(), nodep->name());
-            nodep->replaceWith(newp);
+            if (m_ds.m_dotErr) nodep->unlinkFrBack();  // Avoid circular node loop on errors
+            else nodep->replaceWith(newp);
             pushDeletep(nodep); VL_DANGLING(nodep);
         }
         else {

test_regress/t/t_concat_link_bad.out

@@ -0,0 +1,14 @@
+%Error: t/t_concat_link_bad.v:24: Syntax Error: Not expecting REPLICATE under a DOT in dotted expression
+    assign bar_s = {foo_s, foo_s}.f1;
+                   ^
+%Error: t/t_concat_link_bad.v:24: Syntax Error: Not expecting CONCAT under a REPLICATE in dotted expression
+    assign bar_s = {foo_s, foo_s}.f1;
+                         ^
+%Error: t/t_concat_link_bad.v:24: Syntax Error: Not expecting CONST under a REPLICATE in dotted expression
+    assign bar_s = {foo_s, foo_s}.f1;
+                   ^
+%Warning-IMPLICIT: t/t_concat_link_bad.v:24: Signal definition not found, creating implicitly: 'bar_s'
+    assign bar_s = {foo_s, foo_s}.f1;
+           ^~~~~
+                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_concat_link_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_concat_link_bad.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// Use this file as a template for submitting bugs, etc.
+// This module takes a single clock input, and should either
+//      $write("*-* All Finished *-*\n");
+//      $finish;
+// on success, or $stop.
+//
+// The code as shown applies a random vector to the Test
+// module, then calculates a CRC on the Test module's outputs.
+//
+// **If you do not wish for your code to be released to the public
+// please note it here, otherwise:**
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by ____YOUR_NAME_HERE____.
+
+module t (/*AUTOARG*/);
+
+    typedef logic [3:0] foo_t;
+
+    foo_t foo_s;
+
+    assign bar_s = {foo_s, foo_s}.f1;
+
+endmodule