diff --git a/include/verilated.cpp b/include/verilated.cpp
index b9b408b60..e740066a9 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2396,9 +2396,9 @@ VerilatedVar* VerilatedScope::varFind(const char* namep) const VL_MT_SAFE_POSTIN
 
 void* VerilatedScope::exportFindNullError(int funcnum) VL_MT_SAFE {
     // Slowpath - Called only when find has failed
-    std::string msg = (std::string("Testbench C called '")
-                       +VerilatedImp::exportName(funcnum)
-                       +"' but scope wasn't set, perhaps due to dpi import call without 'context'");
+    std::string msg = (std::string("Testbench C called '") + VerilatedImp::exportName(funcnum)
+                       + "' but scope wasn't set, perhaps due to dpi import call without "
+                       + "'context', or missing svSetScope. See IEEE 1800-2017 35.5.3.");
     VL_FATAL_MT("unknown", 0, "", msg.c_str());
     return NULL;
 }
diff --git a/test_regress/t/t_dpi_export_context_bad.cpp b/test_regress/t/t_dpi_export_context_bad.cpp
new file mode 100644
index 000000000..135bc7d3c
--- /dev/null
+++ b/test_regress/t/t_dpi_export_context_bad.cpp
@@ -0,0 +1,45 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+#include <verilated.h>
+#include VM_PREFIX_INCLUDE
+
+//======================================================================
+
+#if defined(VERILATOR)
+# include "Vt_dpi_export_context_bad__Dpi.h"
+#elif defined(VCS)
+# include "../vc_hdrs.h"
+#elif defined(CADENCE)
+# define NEED_EXTERNS
+#else
+# error "Unknown simulator for DPI test"
+#endif
+
+#ifdef NEED_EXTERNS
+extern "C" {
+    extern void dpix_task();
+}
+#endif
+
+//======================================================================
+
+unsigned int main_time = 0;
+
+double sc_time_stamp() { return main_time; }
+
+VM_PREFIX* topp = NULL;
+
+int main(int argc, char* argv[]) {
+    topp = new VM_PREFIX;
+
+    Verilated::debug(0);
+
+    topp->eval();
+    dpix_task();  // Missing svSetScope
+    return 1;
+}
diff --git a/test_regress/t/t_dpi_export_context_bad.out b/test_regress/t/t_dpi_export_context_bad.out
new file mode 100644
index 000000000..dc2091af3
--- /dev/null
+++ b/test_regress/t/t_dpi_export_context_bad.out
@@ -0,0 +1,2 @@
+%Error: unknown:0: Testbench C called 'dpix_task' but scope wasn't set, perhaps due to dpi import call without 'context', or missing svSetScope. See IEEE 1800-2017 35.5.3.
+Aborting...
diff --git a/test_regress/t/t_dpi_export_context_bad.pl b/test_regress/t/t_dpi_export_context_bad.pl
new file mode 100755
index 000000000..72e2ef077
--- /dev/null
+++ b/test_regress/t/t_dpi_export_context_bad.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    v_flags2 => ["--exe $Self->{t_dir}/t_dpi_export_context_bad.cpp"],
+    make_main => 0,
+    );
+
+execute(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_dpi_export_context_bad.v b/test_regress/t/t_dpi_export_context_bad.v
new file mode 100644
index 000000000..ec52623af
--- /dev/null
+++ b/test_regress/t/t_dpi_export_context_bad.v
@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// Copyright 2020 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+
+module t;
+   export "DPI-C" task dpix_task;
+   task dpix_task();
+      $write("Hello in %m\n");
+   endtask
+endmodule