Fix slice connections of arrays to ports, bug880.

Changes

@@ -21,6 +21,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix UNOPTFLAT change detect on multidim arrays, bug872. [Andrew Bardsley]
 
+****  Fix slice connections of arrays to ports, bug880. [Varun Koyyalagunta]
+
 
 * Verilator 3.868 2014-12-20
 

src/V3Width.cpp

@@ -2072,7 +2072,7 @@ private:
 		// TODO Simple dtype checking, should be a more general check
 		bool hiArray = nodep->exprp()->dtypep()->skipRefp()->castUnpackArrayDType();
 		bool loArray = nodep->modVarp()->dtypep()->skipRefp()->castUnpackArrayDType();
-		if (loArray != hiArray) {
+		if (loArray != hiArray && pinwidth != conwidth) {
 		    nodep->v3error("Illegal "<<nodep->prettyOperatorName()<<","
 				   <<" mismatch between port which is"<<(hiArray?"":" not")<<" an array,"
 				   <<" and expression which is"<<(loArray?"":" not")<<" an array.");

test_regress/t/t_inst_misarray_bad.pl

@@ -11,7 +11,7 @@ compile (
 	 verilator_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-q{%Error: t/t_inst_misarray_bad.v:\d+: Illegal input port connection 'foo', mismatch between port which is not an array, and expression which is an array.
+q{%Error: t/t_inst_misarray_bad.v:\d+: Illegal assignment of constant to unpacked array
 %Error: Exiting due to.*},
 	 );
 

test_regress/t/t_slice_struct_array_modport.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>0,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    );
+
+ok(1);
+1;

test_regress/t/t_slice_struct_array_modport.v

@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Varun Koyyalagunta.
+
+typedef struct packed {
+  logic  p;
+} s_data;
+
+module m1 (output s_data data[1:0]);
+  assign data[0].p = 0;
+  assign data[1].p = 0;
+endmodule
+
+module top (output s_data data[2:0]);
+  m1 m1_inst (.data(data[1:0]));
+endmodule