diff --git a/Changes b/Changes
index 61fae45fc..3a982dd1e 100644
--- a/Changes
+++ b/Changes
@@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 3.919 devel
 
+***   Support 'assume' similar to 'assert', bug1269. [Dan Gisselquist]
+
 ****  Fix tracing example file output, bug1268. [Enzo Chi]
 
 ****  Fix gate optimization out of memory, add --gate-stmts, bug1260. [Alex Solomatnikov]
diff --git a/src/verilog.l b/src/verilog.l
index c39a93038..8b9ea5540 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -437,6 +437,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "always_comb"		{ FL; return yALWAYS_COMB; }
   "always_ff"		{ FL; return yALWAYS_FF; }
   "always_latch"	{ FL; return yALWAYS_LATCH; }
+  "assume"		{ FL; return yASSUME; }
   "assert"		{ FL; return yASSERT; }
   "bind"		{ FL; return yBIND; }
   "bit"			{ FL; return yBIT; }
@@ -490,7 +491,6 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
   "$root"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "alias"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
-  "assume"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "before"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "bins"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "binsof"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
diff --git a/src/verilog.y b/src/verilog.y
index 63ec4c582..31a374b14 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -302,6 +302,7 @@ class AstSenTree;
 %token<fl>		yALWAYS_LATCH	"always_latch"
 %token<fl>		yAND		"and"
 %token<fl>		yASSERT		"assert"
+%token<fl>		yASSUME		"assume"
 %token<fl>		yASSIGN		"assign"
 %token<fl>		yAUTOMATIC	"automatic"
 %token<fl>		yBEGIN		"begin"
@@ -3667,6 +3668,7 @@ clocking_declaration<nodep>:		// IEEE: clocking_declaration  (INCOMPLETE)
 
 labeledStmt<nodep>:
 		immediate_assert_statement		{ $$ = $1; }
+	|	immediate_assume_statement		{ $$ = $1; }
 	;
 
 concurrent_assertion_item<nodep>:	// IEEE: concurrent_assertion_item
@@ -3698,6 +3700,13 @@ immediate_assert_statement<nodep>:	// ==IEEE: immediate_assert_statement
 	|	yASSERT '(' expr ')' stmtBlock yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,$5,$7);   }
 	;
 
+immediate_assume_statement<nodep>:	// ==IEEE: immediate_assume_statement
+	//				// action_block expanded here, for compatibility with AstVAssert
+		yASSUME '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE	{ $$ = new AstVAssert($1,$3,$5, GRAMMARP->createDisplayError($1)); }
+	|	yASSUME '(' expr ')'           yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,NULL,$6); }
+	|	yASSUME '(' expr ')' stmtBlock yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,$5,$7);   }
+	;
+
 //************************************************
 // Covergroup
 
diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v
index e51eed541..3de503741 100644
--- a/test_regress/t/t_assert_basic.v
+++ b/test_regress/t/t_assert_basic.v
@@ -32,6 +32,7 @@ module t (/*AUTOARG*/
 `ifdef FAILING_ASSERTIONS
 	    assert (0) else $info;
 	    assert (0) else $info("Info message");
+	    assume (0) else $info("Info message from failing assumption");
 	    assert (0) else $info("Info message, cyc=%d", cyc);
 	    InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
 	    InErrorBlock: assert (0) else $error("Error....");