forked from github/verilator
Fix dicts declared with ref type (#3960)
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@ -6209,7 +6209,8 @@ private:
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void checkClassAssign(AstNode* nodep, const char* side, AstNode* rhsp,
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AstNodeDType* lhsDTypep) {
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if (VN_IS(lhsDTypep, ClassRefDType) && !VN_IS(rhsp->dtypep(), ClassRefDType)) {
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if (VN_IS(lhsDTypep, ClassRefDType)
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&& !(rhsp->dtypep() && VN_IS(rhsp->dtypep()->skipRefp(), ClassRefDType))) {
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if (auto* const constp = VN_CAST(rhsp, Const)) {
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if (constp->num().isNull()) return;
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}
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21
test_regress/t/t_dict_ref_type.pl
Executable file
21
test_regress/t/t_dict_ref_type.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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68
test_regress/t/t_dict_ref_type.v
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68
test_regress/t/t_dict_ref_type.v
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@ -0,0 +1,68 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo1;
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int x = 1;
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function int get_x;
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return x;
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endfunction
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endclass
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class Foo2;
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int x = 2;
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function int get_x;
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return x;
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endfunction
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endclass
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class Bar;
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typedef Foo1 foo_t;
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protected foo_t m_dict[int];
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function void set(int key);
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foo_t default_value = new;
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m_dict[key] = default_value;
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endfunction
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function foo_t get(int key);
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return m_dict[key];
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endfunction
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endclass
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class Baz #(type T=Foo1);
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protected T m_dict[int];
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function void set(int key);
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T default_value = new;
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m_dict[key] = default_value;
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endfunction
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function T get(int key);
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return m_dict[key];
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endfunction
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endclass
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module t (/*AUTOARG*/
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);
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initial begin
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Bar bar_i = new;
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Baz baz_1_i = new;
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Baz #(Foo2) baz_2_i = new;
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bar_i.set(1);
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baz_1_i.set(2);
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baz_2_i.set(3);
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if (bar_i.get(1).get_x() == 1 &&
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baz_1_i.get(2).get_x() == 1 &&
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baz_2_i.get(3).get_x() == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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endmodule
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