From 052a7e3debff4efe29bd2b459f07e2b8656beff2 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 12 Feb 2015 07:47:45 -0500 Subject: [PATCH] Fix sign extension of pattern members, bug882. --- Changes | 2 ++ src/V3Width.cpp | 2 +- test_regress/t/t_math_signed6.v | 7 +++++-- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/Changes b/Changes index e3b2040b3..e96583643 100644 --- a/Changes +++ b/Changes @@ -25,6 +25,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix mis-optimizing gate assignments in unopt blocks, bug881. [Mike Thyer] +**** Fix sign extension of pattern members, bug882. [Iztok Jeras] + **** Fix clang compile warnings. diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 8a9406e3d..9d1e913a2 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1741,7 +1741,7 @@ private: if (nodep->lhssp()->nextp()) nodep->v3fatalSrc("PatMember value should be singular w/replicates removed"); // Need to propagate assignment type downwards, even on prelim nodep->iterateChildren(*this,WidthVP(nodep->dtypep(),BOTH).p()); - iterateCheck(nodep,"Pattern value",nodep->lhssp(),CONTEXT,FINAL,vdtypep,EXTEND_EXP); + iterateCheck(nodep,"Pattern value",nodep->lhssp(),CONTEXT,FINAL,vdtypep,EXTEND_LHS); } int visitPatMemberRep(AstPatMember* nodep) { uint32_t times = 1; diff --git a/test_regress/t/t_math_signed6.v b/test_regress/t/t_math_signed6.v index e3a0e8645..665222516 100644 --- a/test_regress/t/t_math_signed6.v +++ b/test_regress/t/t_math_signed6.v @@ -3,9 +3,9 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) -module t (/*AUTOARG*/); + module t (/*AUTOARG*/); // signed source logic signed [8-1:0] src; @@ -17,13 +17,16 @@ module t (/*AUTOARG*/); } dst; initial begin + // bug882 // verilator lint_off WIDTH src = 8'sh05; dst = '{s: src, u: src}; + `checkh (dst.s, 16'h0005); `checkh (dst.u, 16'h0005); src = 8'shf5; dst = '{s: src, u: src}; + `checkh (dst.s, 16'hfff5); `checkh (dst.u, 16'hfff5); // verilator lint_on WIDTH