forked from github/verilator
Tests: Add wire-or mux test for future optimization.
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@ -66,4 +66,5 @@ ci/
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/csrc/
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obj_dir.*
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TAGS
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gmon.out
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.*~
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21
test_regress/t/t_const_opt_or.pl
Executable file
21
test_regress/t/t_const_opt_or.pl
Executable file
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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111
test_regress/t/t_const_opt_or.v
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111
test_regress/t/t_const_opt_or.v
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] rd0; // From test of Test.v
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wire [31:0] rd1; // From test of Test.v
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// End of automatics
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wire rden0 = crc[0];
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wire rden1 = crc[1];
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wire [4:0] raddr0 = crc[20:16];
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wire [4:0] raddr1 = crc[28:24];
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Test test(/*AUTOINST*/
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// Outputs
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.rd0 (rd0[31:0]),
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.rd1 (rd1[31:0]),
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// Inputs
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.clk (clk),
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.raddr0 (raddr0[4:0]),
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.raddr1 (raddr1[4:0]),
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.rden0 (rden0),
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.rden1 (rden1));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {rd1, rd0};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc < 10) begin
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sum <= '0;
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hdc97b141ac5d6d7d
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test(/*AUTOARG*/
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// Outputs
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rd0, rd1,
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// Inputs
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clk, raddr0, raddr1, rden0, rden1
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);
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input clk;
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input [4:0] raddr0;
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input [4:0] raddr1;
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input rden0;
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input rden1;
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output reg [31:0] rd0;
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output reg [31:0] rd1;
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reg [31:0] gpr [31:1];
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initial begin
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for (int j=1; j<32; j++ ) begin
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gpr[j] = {8'(j), 8'(j), 8'(j), 8'(j)};
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end
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end
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always_comb begin
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rd0[31:0] = 32'b0;
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rd1[31:0] = 32'b0;
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// Future optimization:
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// Multiple assignments to same variable with OR between them
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// ASSIGN(a, OR(a, aq)), ASSIGN(a, OR(a, bq)) -> ASSIGN(a, OR(a, OR(aq, bq))
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// Skip if we're not const'ing an entire module (IE doing only one assign, etc)
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for (int j=1; j<32; j++ ) begin
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rd0[31:0] |= ({32{rden0 & (raddr0[4:0]== 5'(j))}} & gpr[j][31:0]);
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rd1[31:0] |= ({32{rden1 & (raddr1[4:0]== 5'(j))}} & gpr[j][31:0]);
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end
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end
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endmodule
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