diff --git a/Changes b/Changes
index 42a0560c3..82a4d6a70 100644
--- a/Changes
+++ b/Changes
@@ -29,6 +29,7 @@ Verilator 5.005 devel
 * Fix memory leak in V3Sched, etc. (#3834). [Geza Lore]
 * Fix compatibility with musl libc / Alpine Linux (#3845). [Sören Tempel]
 * Fix empty case items crash (#3851). [rporter]
+* Fix foreach unnamedblk duplicate error (#3885). [Ilya Barkov]
 
 
 Verilator 5.004 2022-12-14
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index b3d693344..11992dd52 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1029,8 +1029,13 @@ class LinkDotFindVisitor final : public VNVisitor {
             // are common.
             for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
                 if (VN_IS(stmtp, Var) || VN_IS(stmtp, Foreach)) {
-                    ++m_modBlockNum;
-                    nodep->name("unnamedblk" + cvtToStr(m_modBlockNum));
+                    std::string name;
+                    do {
+                        ++m_modBlockNum;
+                        name = "unnamedblk" + cvtToStr(m_modBlockNum);
+                        // Increment again if earlier pass of V3LinkDot claimed this name
+                    } while (m_curSymp->findIdFlat(name));
+                    nodep->name(name);
                     break;
                 }
             }
diff --git a/test_regress/t/t_foreach_blkname.pl b/test_regress/t/t_foreach_blkname.pl
new file mode 100755
index 000000000..13587bf85
--- /dev/null
+++ b/test_regress/t/t_foreach_blkname.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_foreach_blkname.v b/test_regress/t/t_foreach_blkname.v
new file mode 100644
index 000000000..768e7697f
--- /dev/null
+++ b/test_regress/t/t_foreach_blkname.v
@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   function void func();
+      int a[2];
+      begin
+         int t;
+      end
+      foreach (a[i]) begin
+      end
+   endfunction
+endmodule