forked from github/verilator
Fix begin_keywords 1800+VAMS, msg1211.
This commit is contained in:
Wilson Snyder
parent
621c51589a
commit
02331e5536
18
Changes
18
Changes
@ -18,12 +18,14 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Add --no-trace-params.
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*** Add assertions on 'unique if', bug725. [Jeff Bush]
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*** Add assertions on 'unique if', bug725. [Jeff Bush]
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*** Add PINCONNECTEMPTY warning. [Holger Waechtler]
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*** Support parameter arrays, bug683. [Jeremy Bennett]
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*** Fix begin_keywords "1800+VAMS", msg1211.
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**** Documentation fixes, bug723. [Glen Gibb]
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**** Support {} in always sensitivity lists, bug745. [Igor Lesik]
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@ -161,17 +163,17 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.847 2013-05-11
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*** Add ALWCOMBORDER warning. [KC Buckenmaier]
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*** Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung]
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**** Support "signal[vec]++".
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**** Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell]
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**** Fix module resolution with __, bug631. [Jason McMullan]
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**** Fix packed array non-zero right index select crash, bug642. [Krzysztof Jankowski]
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**** Fix nested union crash, bug643. [Krzysztof Jankowski]
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@ -487,7 +489,7 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Support $fopen and I/O with integer instead of `verilator_file_descriptor.
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*** Support coverage in -cc and -sc output modes. [John Li]
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Note this requires SystemPerl 1.338 or newer.
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Note this requires SystemPerl 1.338 or newer.
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**** Fix vpi_register_cb using bad s_cb_data, bug370. [by Thomas Watts]
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@ -138,7 +138,7 @@ void yyerrorf(const char* format, ...) {
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%s V95 V01 V05 S05 S09 S12
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%s STRING ATTRMODE TABLE
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%s VA5 SA9 PSL VLT
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%s VA5 SAX PSL VLT
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%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
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%s IGNORE
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@ -179,7 +179,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Verilog 1995 */
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
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{ws} { } /* otherwise ignore white-space */
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{crnl} { NEXTLINE(); } /* Count line numbers */
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/* Extensions to Verilog set, some specified by PSL */
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@ -352,7 +352,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Verilog 2001 */
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<V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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<V01,V05,VA5,S05,S09,S12,SAX,PSL>{
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/* System Tasks */
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"$signed" { FL; return yD_SIGNED; }
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"$unsigned" { FL; return yD_UNSIGNED; }
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@ -383,13 +383,13 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Verilog 2005 */
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<V05,S05,S09,S12,SA9,PSL>{
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<V05,S05,S09,S12,SAX,PSL>{
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/* Keywords */
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"uwire" { FL; return yWIRE; }
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}
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/* System Verilog 2005 */
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<S05,S09,S12,PSL>{
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<S05,S09,S12,SAX,PSL>{
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/* System Tasks */
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"$bits" { FL; return yD_BITS; }
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"$clog2" { FL; return yD_CLOG2; }
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@ -506,7 +506,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* SystemVerilog 2005 ONLY not PSL; different rules for PSL as specified below */
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<S05,S09,S12>{
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<S05,S09,S12,SAX>{
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/* Keywords */
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"assert" { FL; return yASSERT; }
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"const" { FL; return yCONST__LEX; }
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@ -521,7 +521,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* SystemVerilog 2009 */
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<S09,S12,PSL>{
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<S09,S12,SAX,PSL>{
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/* Keywords */
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"global" { FL; return yGLOBAL__LEX; }
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"unique0" { FL; return yUNIQUE0; }
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@ -550,7 +550,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* System Verilog 2012 */
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<S12,PSL>{
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<S12,SAX,PSL>{
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/* Keywords */
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"implements" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
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"interconnect" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
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@ -559,7 +559,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Default PLI rule */
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
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"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng);
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yylval.strp = PARSEP->newString(AstNode::encodeName(str));
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// Lookup unencoded name including the $, to avoid hitting normal signals
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@ -572,7 +572,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* AMS */
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<VA5,SA9>{
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<VA5,SA9,SAX>{
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/* Generic unsupported warnings */
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"above" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
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"abs" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
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@ -666,7 +666,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* PSL */
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/*Entry into PSL; mode change */
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<V95,V01,V05,VA5,S05,S09,S12,SA9>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX>{
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"psl" { yy_push_state(PSL); FL; return yPSL; }
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}
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@ -755,7 +755,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* Meta comments */
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/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
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"/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */
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"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
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"/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; }
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@ -790,11 +790,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Single character operator thingies */
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<V95,V01,V05,VA5,S05,S09,S12,SA9>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX>{
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"{" { FL; return yytext[0]; }
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"}" { FL; return yytext[0]; }
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}
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
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"!" { FL; return yytext[0]; }
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"#" { FL; return yytext[0]; }
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"$" { FL; return yytext[0]; }
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@ -826,7 +826,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* Operators and multi-character symbols */
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/* Verilog 1995 Operators */
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL>{
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"&&" { FL; return yP_ANDAND; }
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"||" { FL; return yP_OROR; }
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"<=" { FL; return yP_LTE; }
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@ -848,7 +848,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Verilog 2001 Operators */
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<V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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<V01,V05,VA5,S05,S09,S12,SAX,PSL>{
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"<<<" { FL; return yP_SLEFT; }
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">>>" { FL; return yP_SSRIGHT; }
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"**" { FL; return yP_POW; }
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@ -858,7 +858,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* SystemVerilog Operators */
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<S05,S09,S12>{
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<S05,S09,S12,SAX>{
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"'" { FL; return yP_TICK; }
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"'{" { FL; return yP_TICKBRA; }
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"==?" { FL; return yP_WILDEQUAL; }
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@ -907,7 +907,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Identifiers and numbers */
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL,VLT>{
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{escid} { FL; yylval.strp = PARSEP->newString
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(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
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return yaID__LEX;
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@ -980,7 +980,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Attributes */
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/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
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<V95,V01,V05,VA5,S05,S09,S12,SA9>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX>{
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"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*), but (* attr_spec
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}
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@ -997,7 +997,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* Preprocessor */
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/* Common for all SYSC header states */
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/* OPTIMIZE: we return one per line, make it one for the entire block */
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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"`accelerate" { } // Verilog-XL compatibility
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"`autoexpand_vectornets" { } // Verilog-XL compatibility
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"`celldefine" { PARSEP->inCellDefine(true); }
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@ -1042,7 +1042,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); }
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"`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); }
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"`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); }
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"`begin_keywords"[ \t]*\"1800+VAMS\" { yy_push_state(SA9); PARSEP->pushBeginKeywords(YY_START); }
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"`begin_keywords"[ \t]*\"1800[+]VAMS\" { yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); } /*Latest SV*/
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"`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
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/* Verilator */
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@ -1073,7 +1073,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Default rules - leave last */
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT>{
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<V95,V01,V05,VA5,S05,S09,S12,SAX,PSL,VLT>{
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"`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); }
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"//"[^\n]* { } /* throw away single line comments */
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. { FL; return yytext[0]; } /* return single char ops. */
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56
test_regress/t/t_dpi_vams.cpp
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56
test_regress/t/t_dpi_vams.cpp
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@ -0,0 +1,56 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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#include <verilated.h>
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#include "Vt_dpi_vams.h"
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//======================================================================
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#if defined(VERILATOR)
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# include "Vt_dpi_vams__Dpi.h"
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#elif defined(VCS)
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# include "../vc_hdrs.h"
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#elif defined(CADENCE)
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# define NEED_EXTERNS
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#else
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# error "Unknown simulator for DPI test"
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#endif
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#ifdef NEED_EXTERNS
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extern "C" {
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extern void dpii_call (double in, double* outp);
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}
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#endif
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void dpii_call (double in, double* outp) {
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*outp = in + 0.1;
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}
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//======================================================================
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unsigned int main_time = 0;
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double sc_time_stamp () {
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return main_time;
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}
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VM_PREFIX* topp = NULL;
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int main (int argc, char *argv[]) {
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topp = new VM_PREFIX;
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Verilated::debug(0);
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topp->in = 1.1;
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topp->eval();
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if (topp->out != 1.2) {
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VL_PRINTF("*-* All Finished *-*\n");
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topp->final();
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} else {
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vl_fatal(__FILE__,__LINE__,"top", "Unexpected results\n");
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}
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return 0;
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}
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21
test_regress/t/t_dpi_vams.pl
Executable file
21
test_regress/t/t_dpi_vams.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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make_top_shell => 0,
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make_main => 0,
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verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"],
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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28
test_regress/t/t_dpi_vams.v
Normal file
28
test_regress/t/t_dpi_vams.v
Normal file
@ -0,0 +1,28 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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//`begin_keywords "VAMS-2.3"
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`begin_keywords "1800+VAMS"
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module t (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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input in;
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wreal in;
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output out;
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wreal out;
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import "DPI-C" context function void dpii_call(input real in, output real out);
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initial begin
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dpii_call(in,out);
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$finish;
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end
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endmodule
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