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Fix error when no modules in , bug1381.

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This commit is contained in:
Wilson Snyder 2019-01-02 18:38:49 -05:00
parent db92ab47ba
commit 0198a2e9f3
4 changed files with 32 additions and 6 deletions
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@ -13,6 +13,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]
**** Fix error when no modules in $unit, bug1381. [Al Grant]
* Verilator 4.008 2018-12-01

10
src/V3LinkLevel.cpp
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@ -101,7 +101,8 @@ void V3LinkLevel::wrapTop(AstNetlist* rootp) {
// TODO the module creation above could be done after linkcells, but
// the rest must be done after data type resolution
wrapTopCell(rootp);
wrapTopPackages(rootp);
V3Global::dumpCheckGlobalTree("wraptop", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 6);
}
void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
@ -150,15 +151,12 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
}
}
}
}
void V3LinkLevel::wrapTopPackages(AstNetlist* rootp) {
// Instantiate all packages under the top wrapper
// This way all later SCOPE based optimizations can ignore packages
AstNodeModule* newmodp = rootp->modulesp();
if (!newmodp || !newmodp->isTop()) rootp->v3fatalSrc("No TOP module found to process");
for (AstNodeModule* modp = rootp->modulesp(); modp; modp=VN_CAST(modp->nextp(), NodeModule)) {
if (VN_IS(modp, Package)) {
if (VN_IS(modp, Package)
&& modp != oldmodp) { // Don't duplicate if didn't find a top module
AstCell* cellp = new AstCell(modp->fileline(),
// Could add __03a__03a="::" to prevent conflict
// with module names/"v"

16
test_regress/t/t_mod_nomod.pl Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2010 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
compile(
);
ok(1);
1;

10
test_regress/t/t_mod_nomod.v Normal file
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@ -0,0 +1,10 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
//bug 1381
logic root_var;
// No module statements....