forked from github/verilator
Internals: Reorder some functions in prep for threads. No functional change.
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Wilson Snyder
parent
dddc51b75c
commit
011e9f3b0a
@ -105,6 +105,8 @@
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class OrderMoveDomScope;
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static bool domainsExclusive(const AstSenTree* fromp, const AstSenTree* top);
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//######################################################################
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// Functions for above graph classes
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@ -371,9 +373,9 @@ public:
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virtual ~OrderClkMarkVisitor() {}
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};
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//######################################################################
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// The class used to check if the assignment has clocker inside.
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// The class checks if the assignment generates a clock.
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class OrderClkAssVisitor : public AstNVisitor {
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private:
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bool m_clkAss; // There is signals marked as clocker in the assignment
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@ -526,7 +528,6 @@ private:
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void processMoveReadyOne(OrderMoveVertex* vertexp);
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void processMoveDoneOne(OrderMoveVertex* vertexp);
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void processMoveOne(OrderMoveVertex* vertexp, OrderMoveDomScope* domScopep, int level);
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static bool domainsExclusive(const AstSenTree* fromp, const AstSenTree* top);
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string cfuncName(AstNodeModule* modp, AstSenTree* domainp, AstScope* scopep, AstNode* forWhatp) {
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modp->user3Inc();
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@ -997,7 +998,44 @@ public:
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};
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//######################################################################
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// Clock propagation
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// General utilities
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static bool domainsExclusive(const AstSenTree* fromp, const AstSenTree* top) {
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// Return 'true' if we can prove that both 'from' and 'to' cannot both
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// be active on the same eval pass, or false if we can't prove this.
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//
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// For now, this only detects the case of 'always @(posedge clk)'
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// and 'always @(negedge clk)' being exclusive.
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//
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// Are there any other cases we need to handle? Maybe not,
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// because these are not exclusive:
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// always @(posedge A or posedge B)
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// always @(negedge A)
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//
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// ... unless you know more about A and B, which sounds hard.
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const AstSenItem* fromSenListp = VN_CAST(fromp->sensesp(), SenItem);
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const AstSenItem* toSenListp = VN_CAST(top->sensesp(), SenItem);
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// If clk gating is ever reenabled, we may need to update this to handle
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// AstSenGate also.
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if (!fromSenListp) fromp->v3fatalSrc("sensitivity list item is not an AstSenItem");
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if (!toSenListp) top->v3fatalSrc("sensitivity list item is not an AstSenItem");
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if (fromSenListp->nextp()) return false;
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if (toSenListp->nextp()) return false;
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const AstNodeVarRef* fromVarrefp = fromSenListp->varrefp();
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const AstNodeVarRef* toVarrefp = toSenListp->varrefp();
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if (!fromVarrefp || !toVarrefp) return false;
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// We know nothing about the relationship between different clocks here,
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// so give up on proving anything.
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if (fromVarrefp->varScopep() != toVarrefp->varScopep()) return false;
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return fromSenListp->edgeType().exclusiveEdge(toSenListp->edgeType());
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}
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//######################################################################
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// OrderVisitor - Clock propagation
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void OrderVisitor::processInputs() {
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m_graph.userClearVertices(); // Vertex::user() // 1 if input recursed, 2 if marked as input, 3 if out-edges recursed
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@ -1076,7 +1114,7 @@ void OrderVisitor::processInputsOutIterate(OrderEitherVertex* vertexp, VertexVec
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}
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//######################################################################
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// Circular detection
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// OrderVisitor - Circular detection
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void OrderVisitor::processCircular() {
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// Take broken edges and add circular flags
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@ -1245,7 +1283,7 @@ void OrderVisitor::processDomainsIterate(OrderEitherVertex* vertexp) {
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}
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//######################################################################
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// Move graph construction
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// OrderVisitor - Move graph construction
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void OrderVisitor::processEdgeReport() {
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// Make report of all signal names and what clock edges they have
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@ -1277,12 +1315,8 @@ void OrderVisitor::processEdgeReport() {
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for (std::deque<string>::iterator it=report.begin(); it!=report.end(); ++it) {
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*logp<<(*it)<<endl;
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}
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}
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//######################################################################
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// Move graph construction
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void OrderVisitor::processMoveClear() {
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OrderMoveDomScope::clear();
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m_pomWaiting.reset();
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@ -1314,41 +1348,6 @@ void OrderVisitor::processMoveBuildGraph() {
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}
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}
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bool OrderVisitor::domainsExclusive(const AstSenTree* fromp,
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const AstSenTree* top) {
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// Return 'true' if we can prove that both 'from' and 'to' cannot both
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// be active on the same eval pass, or false if we can't prove this.
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//
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// For now, this only detects the case of 'always @(posedge clk)'
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// and 'always @(negedge clk)' being exclusive.
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//
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// Are there any other cases we need to handle? Maybe not,
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// because these are not exclusive:
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// always @(posedge A or posedge B)
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// always @(negedge A)
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//
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// ... unless you know more about A and B, which sounds hard.
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const AstSenItem* fromSenListp = VN_CAST(fromp->sensesp(), SenItem);
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const AstSenItem* toSenListp = VN_CAST(top->sensesp(), SenItem);
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// If clk gating is ever reenabled, we may need to update this to handle
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// AstSenGate also.
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if (!fromSenListp) fromp->v3fatalSrc("sensitivity list item is not an AstSenItem");
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if (!toSenListp) top->v3fatalSrc("sensitivity list item is not an AstSenItem");
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if (fromSenListp->nextp()) return false;
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if (toSenListp->nextp()) return false;
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const AstNodeVarRef* fromVarrefp = fromSenListp->varrefp();
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const AstNodeVarRef* toVarrefp = toSenListp->varrefp();
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if (!fromVarrefp || !toVarrefp) return false;
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// We know nothing about the relationship between different clocks here,
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// so give up on proving anything.
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if (fromVarrefp->varScopep() != toVarrefp->varScopep()) return false;
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return fromSenListp->edgeType().exclusiveEdge(toSenListp->edgeType());
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}
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void OrderVisitor::processMoveBuildGraphIterate (OrderMoveVertex* moveVxp, V3GraphVertex* vertexp, int weightmin) {
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// Search forward from given logic vertex, making new edges based on moveVxp
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for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
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@ -1388,7 +1387,7 @@ void OrderVisitor::processMoveBuildGraphIterate (OrderMoveVertex* moveVxp, V3Gra
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}
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//######################################################################
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// Moving
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// OrderVisitor - Moving
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void OrderVisitor::processMove() {
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// The graph routines have already sorted the vertexes and edges into best->worst order
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@ -1572,7 +1571,7 @@ inline void OrderMoveDomScope::movedVertex(OrderVisitor* ovp, OrderMoveVertex* v
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}
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//######################################################################
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// Top processing
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// OrderVisitor - Top processing
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void OrderVisitor::process() {
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// Dump data
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@ -330,6 +330,7 @@ public:
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virtual OrderMoveVertex* clone(V3Graph* graphp) const {
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return new OrderMoveVertex(graphp, *this);
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}
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// METHODS
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virtual OrderVEdgeType type() const { return OrderVEdgeType::VERTEX_MOVE; }
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virtual string dotColor() const {
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if (logicp()) {
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@ -350,7 +351,6 @@ public:
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}
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return nm;
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}
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// ACCESSORS
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OrderLogicVertex* logicp() const { return m_logicp; }
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bool isWait() const { return m_state==POM_WAIT; }
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void setReady() {
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