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Fix size-changing cast on packed struct, bug993.

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Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
Johan Bjork 2015-11-06 19:12:17 -05:00 committed by Wilson Snyder
parent 7850f49963
commit 0081ce4a75
3 changed files with 15 additions and 0 deletions
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@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix real parameters causing bad module names, bug992. [Johan Bjork]
**** Fix size-changing cast on packed struct, bug993. [Johan Bjork]
* Verilator 3.878 2015-11-01

3
src/V3Width.cpp
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@ -1017,6 +1017,9 @@ private:
if (width < 1) { nodep->v3error("Size-changing cast to zero or negative size"); width=1; }
nodep->lhsp()->iterateAndNext(*this,WidthVP(SELF,PRELIM).p());
AstBasicDType* underDtp = nodep->lhsp()->dtypep()->castBasicDType();
if (!underDtp) {
underDtp = nodep->lhsp()->dtypep()->basicp();
}
if (!underDtp) {
nodep->v3error("Unsupported: Size-changing cast on non-basic data type");
underDtp = nodep->findLogicBoolDType()->castBasicDType();

10
test_regress/t/t_cast.v
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@ -8,6 +8,15 @@ module t;
typedef logic [3:0] mc_t;
typedef mc_t tocast_t;
typedef struct packed {
logic [15:0] data;
} packed_t;
packed_t pdata;
assign pdata.data = 16'h1234;
logic [7:0] logic8bit;
assign logic8bit = $bits(logic8bit)'(pdata >> 8);
mc_t o;
logic [15:0] allones = 16'hffff;
@ -31,6 +40,7 @@ module t;
(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
initial begin
if (logic8bit != 8'h12) $stop;
if (4'shf > 4'sh0) $stop;
if (signed'(4'hf) > 4'sh0) $stop;
if (4'hf < 4'h0) $stop;