verilator/test_regress/t/t_unopt_converge_unopt_bad.out

%Warning-UNOPTFLAT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Circular combinational logic: 'x'
   19 |    output x;    
      |           ^
                    ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
                    ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                    t/t_unopt_converge.v:19:11:      Example path: x
                    t/t_unopt_converge.v:23:9:      Example path: ASSIGNW
                    t/t_unopt_converge.v:19:11:      Example path: x
%Error: Exiting due to
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`%Warning-UNOPTFLAT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Circular combinational logic: 'x'`
Add GCC10-style line number prefix when showing source text for errors. 2020-04-04 00:07:46 +00:00			`19 \| output x;`
			`\| ^`
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest`
			`... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.`
			`t/t_unopt_converge.v:19:11: Example path: x`
DFG: handle simple always blocks 2022-10-01 11:28:16 +00:00			`t/t_unopt_converge.v:23:9: Example path: ASSIGNW`
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`t/t_unopt_converge.v:19:11: Example path: x`
Tests: Favor golden files over long regexps. No functional change. 2018-11-03 18:59:04 +00:00			`%Error: Exiting due to`