forked from github/verilator
18 lines
418 B
Systemverilog
18 lines
418 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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wire a;
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bufif1 (strong0, strong1) (a, 1'b1, 1'b1);
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always begin
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if (a) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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