forked from github/verilator
5 lines
199 B
Plaintext
5 lines
199 B
Plaintext
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%Error: t/t_force_bad_rw.v:14:20: Unsupported: Signals used via read-write reference cannot be forced
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14 | foreach (ass[index]) begin
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| ^~~~~
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%Error: Exiting due to
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