forked from github/verilator
22 lines
529 B
Systemverilog
22 lines
529 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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function automatic string broken_case(input string some_string);
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case(some_string)
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"alpha": return "alpha";
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default: return "beta";
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endcase
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endfunction
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initial begin
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$display(broken_case("gamma"));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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