verilator/test_regress/t/t_display_qqq.v

18 lines
375 B
Systemverilog
Raw Normal View History

2022-11-18 01:37:51 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
$display("""First "quoted"\nsecond\
third
fourth""");
$write("*-* All Finished *-*\n");
$finish;
end
endmodule