2019-06-30 20:46:48 +00:00
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 15:24:24 +00:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2006 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2019-06-30 20:46:48 +00:00
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#include <iostream>
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#include <verilated.h>
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#include "Vt_multitop_sig.h"
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2021-03-12 17:37:26 +00:00
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#include "TestCheck.h"
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2021-02-17 01:34:44 +00:00
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double sc_time_stamp() { return 0; }
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2021-03-12 17:37:26 +00:00
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int errors = 0;
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2019-06-30 20:46:48 +00:00
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2019-11-10 01:35:12 +00:00
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int main(int argc, char* argv[]) {
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Vt_multitop_sig* topp = new Vt_multitop_sig("");
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2019-06-30 20:46:48 +00:00
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Verilated::debug(0);
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{
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topp->a__02Ein = 0;
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topp->b__02Ein = 0;
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topp->uniq_in = 0;
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topp->eval();
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2021-03-12 17:37:26 +00:00
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TEST_CHECK_EQ(topp->a__02Eout, 1);
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TEST_CHECK_EQ(topp->b__02Eout, 0);
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TEST_CHECK_EQ(topp->uniq_out, 1);
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2019-06-30 20:46:48 +00:00
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topp->a__02Ein = 1;
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topp->b__02Ein = 1;
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topp->uniq_in = 1;
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topp->eval();
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2021-03-12 17:37:26 +00:00
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TEST_CHECK_EQ(topp->a__02Eout, 0);
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TEST_CHECK_EQ(topp->b__02Eout, 1);
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TEST_CHECK_EQ(topp->uniq_out, 0);
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2019-06-30 20:46:48 +00:00
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}
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2020-11-17 11:37:55 +00:00
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topp->final();
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VL_DO_DANGLING(delete topp, topp);
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2019-06-30 20:46:48 +00:00
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printf("*-* All Finished *-*\n");
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2021-03-12 17:37:26 +00:00
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return errors ? 10 : 0;
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2019-06-30 20:46:48 +00:00
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}
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