forked from github/verilator
3 lines
201 B
Plaintext
3 lines
201 B
Plaintext
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%Error: SystemC's sc_set_time_resolution is 10^-9, which does not match Verilog timeprecision 10^-12. Suggest use 'sc_set_time_resolution(1ps)', or Verilator '--timescale-override 1ns/1ns'
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Aborting...
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