forked from github/verilator
61 lines
1.3 KiB
Coq
61 lines
1.3 KiB
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (clk);
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input clk;
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integer cyc=0;
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typedef struct packed {
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bit b1;
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bit b0;
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} strp_t;
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typedef struct packed {
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strp_t x1;
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strp_t x0;
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} strp_strp_t;
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typedef bit [2:1] arrp_t;
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typedef arrp_t [4:3] arrp_arrp_t;
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typedef strp_t [4:3] arrp_strp_t;
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typedef bit arru_t [2:1];
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typedef arru_t arru_arru_t [4:3];
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typedef arrp_t arru_arrp_t [4:3];
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typedef strp_t arru_strp_t [4:3];
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strp_t v_strp;
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strp_strp_t v_strp_strp;
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arrp_t v_arrp;
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arrp_arrp_t v_arrp_arrp;
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arrp_strp_t v_arrp_strp;
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arru_t v_arru;
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arru_arru_t v_arru_arru;
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arru_arrp_t v_arru_arrp;
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arru_strp_t v_arru_strp;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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v_strp <= ~v_strp;
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v_strp_strp <= ~v_strp_strp;
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v_arrp_strp <= ~v_arrp_strp;
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v_arrp <= ~v_arrp;
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v_arrp_arrp <= ~v_arrp_arrp;
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for (integer b=3; b<=4; b++) begin
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v_arru[b] <= ~v_arru[b];
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v_arru_strp[b] <= ~v_arru_strp[b];
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v_arru_arrp[b] <= ~v_arru_arrp[b];
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for (integer a=3; a<=4; a++) begin
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v_arru_arru[a][b] = ~v_arru_arru[a][b];
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end
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end
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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