forked from github/verilator
43 lines
1017 B
Systemverilog
43 lines
1017 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(
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output logic [255:0] data_out
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);
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localparam int NUM_STAGES = 3;
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/* verilator lint_off ALWCOMBORDER */
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/* verilator lint_off UNOPTFLAT */
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`define INPUT 256'hbabecafe
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logic [255:0] stage_data [NUM_STAGES+1];
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genvar stage;
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generate
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always_comb begin
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stage_data[0] = `INPUT;
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end
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for (stage = 0; stage < NUM_STAGES; ++stage) begin : stage_gen
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always_comb begin
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stage_data[stage+1] = stage_data[stage];
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end
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end
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endgenerate
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/* verilator lint_on UNOPTFLAT */
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/* verilator lint_on ALWCOMBORDER */
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always_comb begin
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data_out = stage_data[NUM_STAGES];
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if (data_out !== `INPUT) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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