forked from github/verilator
47 lines
1.2 KiB
Systemverilog
47 lines
1.2 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2022 by Geza Lore. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// This hits a case where parameter specialization of recursive modules
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// used to yield a module list that was not topologically sorted, which
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// then caused V3Inline to blow up as it assumes that.
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module top #(
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parameter N=8
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) (
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input wire [N-1:0] i,
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output wire [N-1:0] o,
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output wire [N-1:0] a
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);
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sub #(.N(N)) inst(.i(i), .o(a));
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generate if (N > 1) begin: recursive
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top #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2]), .a());
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top #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0]), .a());
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end else begin: base
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assign o = i;
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end endgenerate
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endmodule
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module sub #(
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parameter N = 8
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) (
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input wire [N-1:0] i,
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output wire [N-1:0] o
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);
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generate if (N > 1) begin: recursive
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sub #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2]));
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sub #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0]));
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end else begin: base
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assign o = i;
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end endgenerate
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endmodule
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