forked from github/verilator
17 lines
332 B
Systemverilog
17 lines
332 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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package foo;
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endpackage
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package bar;
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static int baz;
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endpackage
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module t;
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int baz = foo::bar::baz;
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endmodule
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