forked from github/verilator
21 lines
431 B
Systemverilog
21 lines
431 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface class Icls;
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localparam IP = 1;
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typedef int i_t;
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endclass
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class Cls implements Icls;
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function void f;
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$display(IP); // Bad
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endfunction
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endclass
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module t (/*AUTOARG*/);
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Cls c;
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endmodule
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