forked from github/verilator
25 lines
529 B
Systemverilog
25 lines
529 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface class Icls1;
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pure virtual function int icfboth;
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endclass
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interface class Icls2;
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pure virtual function int icfboth;
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endclass
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interface class IclsBoth extends Icls1, Icls2;
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// Bad collision on icfboth
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endclass
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class Cls implements IclsBoth;
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endclass
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module t (/*AUTOARG*/);
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Cls c;
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endmodule
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