forked from github/verilator
17 lines
364 B
Systemverilog
17 lines
364 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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function void func();
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int a[2];
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begin
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int t;
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end
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foreach (a[i]) begin
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end
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endfunction
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endmodule
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