forked from github/verilator
32 lines
694 B
Systemverilog
32 lines
694 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Cls #(int PARAM = 1);
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parameter OTHER = 12;
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endclass
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class Other extends Cls#(); // Ok
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endclass
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class OtherMaybe extends Cls; // Questionable but others do not warn
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endclass
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module t (/*AUTOARG*/);
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typedef Cls#(2) Cls2_t; // Ok
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typedef Cls ClsNone_t; // Ok
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Cls c; // Ok
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initial begin
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if (Cls#()::OTHER != 12) $stop; // Ok
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if (Cls2_t::OTHER != 12) $stop; // ok
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if (Cls::OTHER != 12) $stop; // Bad #() required
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end
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endmodule
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