forked from github/verilator
29 lines
731 B
Systemverilog
29 lines
731 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class T;
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function automatic void print_str(input string a_string);
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$display(a_string);
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endfunction
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static function automatic void static_print_str(input string a_string);
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$display(a_string);
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endfunction
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endclass
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initial begin
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T t_c = new;
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t_c.print_str("function though member");
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t_c.static_print_str("static function through member");
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T::static_print_str("static function through class");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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