forked from github/verilator
16 lines
353 B
Systemverilog
16 lines
353 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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endclass
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class Bar extends Foo;
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int m_field = get_1();
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function int get_1();
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return 1;
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endfunction
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endclass
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