forked from github/verilator
21 lines
485 B
Systemverilog
21 lines
485 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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const int aconst = 10;
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static const int astatic = 20;
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endclass
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module t;
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initial begin
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Cls c = new;
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if (c.aconst !== 10) $stop;
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if (Cls::astatic !== 20) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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