forked from github/verilator
14 lines
322 B
Systemverilog
14 lines
322 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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casex (1'bx) inside
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default: $stop;
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endcase
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end
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endmodule
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